Power Integrity Optimization Cuts RF Substrate Noise

Our main focus is on dynamic voltage drop at 16-14-10nm and beyond, but the rise of the Internet of Things (IoT) prompted me to share some silicon measurement results that are relevant to the RF design community. Normally, power integrity (PI) is looked at in the time domain, but in this work we looked at it from a frequency spectrum perspective. Silicon measurements prove how shaping the dynamic current demand waveform, and thereby changing the noise spectrum, can significantly improve the operating conditions for RF circuits on-chip.

Digital Noise and RF Circuits
A key concern in mixed-signal integration is noise from synchronous digital circuits conveyed into sensitive analog circuits on the same substrate. Pathways for noise propagation include the power supply and the common silicon substrate. Supply domain separation, where possible, minimizes that concern, while component cost constraints often limit fabrication process choices. Substrate noise is, hence, a significant detrimental component in such ICs. Despite careful physical design, noise conducted through the substrate often limits RF performance, and RF designers look for even 0.5 to 1dB improvements. Everything counts when you try to meet specs and increase range at the same power and area budget.

An effective method for noise reduction is to address it at the source—synchronous switching and corresponding supply noise. Digital circuits operate with a synchronizing clock signal. Clock edges control the transition of states of digital flip-flop circuits. These circuits draw significant supply current that leads to noise as it flows through supply network impedance. The power delivery network R and L, in particular, contribute to R*i and L*di/dt noise.

A concentration of logic circuits switching together, at a clock edge, leads to large supply current peaks, and to significant noise generation. Careful modulation of this synchronicity, through clock latency scheduling, helps to spread supply current demand and mitigate noise. Teklatech’s FloorDirector was used for this challenge in a 130nm test chip, SCREAMER, and substrate noise measurements were done to confirm the improvements.

Figure 1: SCREAMER test chip layout view

FloorDirector Optimization
The SCREAMER test chip (Figure 1) comprised four mixed-signal macros, M0 through M3, differentiated by their clock distribution latencies (M3 also used double-edged clocking). These macros included guard rings to prevent noise injection from external sources. The chip also implemented guard ring bars separating macros from each other. Substrate p-taps and probe points within the macros, at identical locations, provided noise data.

FloorDirector is a Dynamic Voltage Drop (DVD) minimization tool. It employs proprietary clock latency scheduling algorithms that optimize clock distribution for reduced DVD, which is then evaluated in the time domain. An advanced capability is its frequency domain mode that minimizes noise in a specified spectral band. Macro M0 had its timing closure conducted in an industry standard tool, and FloorDirector implemented clock latency optimization in M1 (conservative optimization) and M2 (aggressive optimization).

In SCREAMER, the target was in the 790 to 910MHz band around the 850MHz GSM frequency. The tool determined a set of clock latencies that minimized noise power spectral amplitude in the given band. The digital clock frequency in SCREAMER was 50MHz, and noise spectral density is plotted in its harmonics (100, 150, 200 etc.).
Plots in Figure 2 below show noise power in measured dBm over the spectral range. Focus on the M0-M2 macros which are using the exact same architecture.

Figure 2: Substrate noise spectra and peak for macros M0-M3

Results
All noise plots for FloorDirector optimized macros fall below the baseline macro M drawn in solid blue. Plotted in dBm, referenced to 1 milliwatt power, a change of -3dBm corresponds to half the noise power. Note, in particular, large noise reduction for M1 (Red) and M3 (Purple) at 150MHz. Third-harmonic noise is a distinct signature of digital synchronous switching. This reduction in noise at the third harmonic confirms the application and benefit of FloorDirector to switching noise. Macro M2 (Green) also displays lower third-harmonic noise. (Dissimilar to others, macro M3 in purple demonstrates an increase in second-harmonic noise at 100MHz, confirming a change in architecture to double-edged clocking.)

At 850MHz, FloorDirector optimized macros M1 and M2 show between 6dBm and 11dBm of noise reduction [1]. Measured peak-to-peak substrate noise also shows between 10 and 30% reduction for all macros.

We have made the full abstract available for download here. Substrate noise is a different aspect of power integrity, and I hope you find it an interesting read.