Power Trip Advisor

By Geoffrey James
There’s never been a greater demand for power-efficient silicon. As consumer electronic devices get smaller, with increased functionality, battery power becomes a premium resource. At the same time, “Green IT” is a major corporate trend, and the best way to be environmentally sensitive (while saving on energy costs) is to buy technology that ekes the maximum computing oomph out of every watt it eats.

The bad news is that today’s small geometries and touchy chip manufacturing processes can turn energy efficiency into a design nightmare. The good news is a wealth of techniques and tools are emerging that make chips less power-hungry, creating a generation of chip designs that satisfy the need for more compute power without squandering the electrical power that makes it work.

The low-power challenge
When it comes to lowering the power consumption of semiconductors, Moore’s law is a double-edged sword. On one hand, the smaller the circuitry, the more computing and memory bang you get for your energy buck. Consider: a typical PC sold today consumes about the same amount electrical power as a PC sold 25 years ago, but has enough computer power to replace ten thousand vintage 1984 units.

On the other hand, Moore’s law also creates a real problem when it comes to power management: leakage. Chips expend electrical power in two ways. The first is dynamic power, which is the electrical power it takes to make the chip do what it’s supposed to do – like turn switches on and off. The second is static power (aka leakage), which is the heat that circuits generate as a byproduct of having electrical energy flowing through them.

In ancient times (i.e. back when 180nm was considered state-of-the-art), designers could largely ignore static power because it gobbled up only a tiny percentage of the electrical power flowing into the chip. But as geometries have shrunk, static power has become ever more intrusive. “With a small enough geometry and a big enough chip, we have to deal with as much as 20 percent of the electrical power dissipated by leakage,” says George Zimmerman, CTO at Solarflare, a maker of 10 Gigabyte per second Ethernet controllers.

Leakage also can make other, nearby circuits act unpredictably – always a bad thing – and that unpredictability is determined not just by the chip’s layout, but by the specific manufacturing process used to generate the chip.

“There are variances in circuit behavior even among the different manufacturing lines within a given foundry,” explains Brian Leibowitz, senior member of technical staff for circuits design at the memory IP vendor Rambus.

Even dynamic power presents challenges at the smaller geometries, mostly because today’s SoCs integrate so much content onto a single piece of silicon. “Different components used to live on different chips, each with its own power requirement,” explains EDA guru Gary Smith. “SoCs force designers to manage different power requirements on a single chip.” And, just to make things even more complicated, the way circuits use dynamic power can vary, especially at the newest nodes, based upon the characteristics of the individual manufacturing process.

Techniques and tricks
There are several ways to make chips more power efficient.

First, a designer can make sure a circuit only does the minimum amount of work (i.e. switching) when it’s actually in use. This is typically accomplished through clock-gating — adding additional logic to disable portions of the circuitry so that its switches do not change state unnecessarily. This causes the switching power consumption to drop to zero, but does not (alas!) eliminate leakage, which continues as long as the circuit remains active, according to Darren Jones, engineering director at the CPU IP company MIPS.

A more comprehensive approach is to completely power down a block of circuits when they’re not needed. For example, if a quad-core CPU is running a simple spreadsheet, it may be using only 10% of a single CPU core. In that case, cutting the power to the other three cores vastly reduces the power consumption of the entire chip. Powering a block down intelligently, however, requires considerable design savvy. There’s always a danger that the powered-down block might get out of sync with the rest of the chip or, even worse, get its circuits fried when the power comes rushing back.

A variety of clever, but less radical, techniques also serve to reduce, if not eliminate, power consumption. For example, you can lay down a CPU block that’s got more potential muscle than you really need and then run that block at lower power. As a result, you get less processing power out of the block than its full potential, but because the block is optimized to run faster (and therefore hotter), the net result is far less leakage. “This technique can be applied in a wide range of embedded designs,” explains Jones.

Another sophisticated approach is “dynamic voltage and frequency scaling” where the chip (and surrounding system) selects the amount of power to feed into each block, based upon the kind of processing that the block in question is expected to accomplish. “That way you end up paying the full leakage cost only when each block is working its hardest,” says Jones.

However, these fancy techniques, while useful, aren’t free. There’s design overhead because the operating system running atop the chip must understand exactly what’s going on, lest it suddenly discover that an expected resource is no longer available. That means the chip designer must think architecturally from the start, and look at the entire target system, rather than simply the characteristics of the chip itself.

There are also tricks that can be played at the system level. Power transistors are a perfect example. As any system designer knows, feeding a smooth flow of electrical power to a chip requires a power transistor either on the board or (more rarely) on the chip itself. Even though power transistors are typically built using fairly large geometries, they can be shockingly inefficient, losing as much as 40% of their incoming power to leakage. Fortunately, it’s possible to build and tune such transistors so that they approach efficiencies as high as 90%, according to Dermott Lynch, the vice president of sales for Silicon Frontline, a company that provides power transistor test and analysis.

EDA to the rescue
While chip designers thus have a variety of techniques to draw upon, the design process is not always straightforward, and must account for variances in manufacturing processing, according to Sudhakar Jilla, director of marketing for the place and route group at Mentor Graphics. “To do this correctly, you essentially need to think about the problem at all levels, from the first initial ESL architecture, all the way down to the final tape out,” he says.

Because of this, EDA firms have built power management capabilities into a wide range of their software tools. Synopsys, for example, has created a solution called Eclypse (see Figure 1) that helps manage power issues throughout the entire design flow, according to David Hsu, the company’s director of solutions marketing. “We’re finding that our customers are deeply concerned about these issues and are looking for a complete solution that spans the entire tool flow,” he explains.

Figure 1: Synopsys' approach to cutting the power.

In addition, there are plenty of smaller companies helping designers to cram as much efficiency as possible into their chips. The company Mellanox, for example, has a tool that allows companies to explore the power consumption tradeoffs between running a CPU at low power continuously and running it in short bursts of high power, based upon the intended usage of the final device, according to Ghislain Kaiser, the company’s CEO and founder.

Such tools work well with the larger suites because the EDA industry had the foresight to settle on a design standard, Unified Power Format (aka UPF or IEEE P1801). “It provides a single power specification for your chip defined in a single file,” explains Arvind Narayanan, Olympus-SoC product manager at Mentor Graphics. “This allows Mentor’s tools to be applied across a wide range of design environments.”

(Editor’s Note: UPF is backed by Accellera and is supported by Mentor Graphics, Synopsys and Magma. A similar standard called the Common Power Format, put forth by Si2 is supported by Cadence.)

While today’s chip designers are successfully coping with low power requirements, the future may prove more challenging, according to Cary Chin, director of technical marketing for low-power solutions at Synopsys. “At 65nm and 45nm, it’s not unusual to see chip designs where dynamic power and static power are gobbling up equal amounts of energy,” he explains. “At even smaller nodes, designers are worried that the leakage problem may get worse.”

Even so, the semiconductor industry, along with the EDA firms that help them, has overcome similar challenges in the past, Smith points out. “When it comes to solving problems, the creativity of this industry is truly phenomenal. If there’s a way to manage power effectively as we get to the smaller nodes, you can rest assured that some smart group of designers will figure it out.”