Preparing For 3DX

By Aveek Sarkar
Undoubtedly we live in the age of mobility—smartphones, tablets, and ultra-books have transformed the way we work, live, and communicate. The worldwide smartphone market’s forecasted 24% CAGR, between 2010 and 2015 provides unique opportunities1. In emerging economies, more than 1 billion consumers are ready for the next new mobile platform2. Success in this market demands rapid evolution of the underlying software, system, and IC architecture. SoCs for mobile handsets are going beyond Moore’s Law in order to address functionality needs while meeting power, performance and price goals. However, more must be done to evolve beyond single-die, or PoP architectures that have fueled the mobile revolution so far.

While the shift to integrating chips in a true 3D manner had false starts in the past, the benefits are apparent, especially to meet the above challenges. With 50% of the world’s top 20 semiconductor companies already working on technology for a stacked-die product, 3D-IC is real. A recent forecast estimates the 3D-IC market to reach $6.55 billion by 20163, so quick progress has to be made to enable the success of this technology. Standardizing the way data can be shared between the various design teams and EDA solutions providers to enable comprehensive 3D/2.5D simulation coverage is one necessary step in that direction.

Before such benefits can be realized, several business and technology challenges must be solved. Considerable progress has been made during the past 10 years, but a cohesive and coordinated strategy will accelerate the work past the remaining challenges, to design and manufacture these systems in a cost-effective manner. For example, it is still a matter of debate regarding which parts of the manufacturing process are done in a wafer fab and which are done in a packaging house and just who will be liable for yields4.

For some design and simulation tools, incremental changes must be done to enable 3D/2.5D designs beyond what they do for 2D. For these tool providers, product extensions will sufficiently meet the new requirements. However, power delivery integrity, thermal modeling, reliability impact analysis, and chip-to-chip signal integrity simulations will require new frameworks beyond traditional 2D solutions and methods because the presence of multiple chips in close proximity can introduce new, or exacerbate existing, challenges in these areas. Offering 3D-IC EDA solutions to address these simulation requirements demand time and resource investments. The challenges go beyond the obvious need to handle the capacity required to simulate multi-die designs. The chips in a 3D/2.5 stack are typically on different process technologies, may have TSVs implanted in them, with connections via thousands of micro-bumps. All of these must be factored in while performing a unified multi-die, cross-coupled, multi-physics simulation of the 3D/2.5D system.

Stacking multiple chips in close proximity inside the same package significantly reduces the parasitics that power and signal lines otherwise face in a traditional PCB-based design. This reduces power consumption through the use of sub-1V supplies (by up to 75%), and using smaller I/O drivers while achieving higher bandwidth (two orders of magnitude). To help mitigate power, thermal and reliability challenges from different ICs working in close proximity, active partnership is needed between different IC design teams who may not be willing to share all the relevant data to protect their IP. Design methodology shifts and mind-set transformations are needed to bridge this gap.

Although making stacked-die designs a mainstream reality will require extensive industry cooperation to drive the creation and adoption of standards well beyond the traditional supply chain, similar to the transformation of the IP business model, collaboration should not be limited between IC design teams and tool providers. It also must include foundries and package manufacturers.

As a point of reference, Apache has been working for more than three years with IC design and foundry partners to deliver IC and package/PCB simulation platforms, including the RedHawk-3DX extension, specifically architected to solve power, thermal, reliability and signal integrity challenges for stacked multi-die designs5,6,7. For EDA tool suppliers to keep pace with upcoming market demands, we should already be collaborating with customers and partners to deliver advanced 3D modeling and simulation solutions to ease the transition from 2D to 2.5D, and eventually to 3D.

References:
1 Coda Research Consultancy Ltd, “Worldwide Smartphone Sales Forecast to 2015”, May 2010.
2 NielsenWire, “Smartphone sales soar in Brazil as affordable devices reach more customers”, The Nielson Company, August 2010.
3 Marketsandmarkets: “Global 3D IC and TSV Interconnect Market worth $6.55 billion by 2016”, April 2012.
4 Matt Nowak, Qualcomm, “Price cited as top challenge in 3-D stacks”, EE Times, October 2011.
5 Riquet et al, “Analysis of Power Delivery network of Multiple Stacked ASICs using TSV and Micro-bumps”, DAC User Track, 2010.
6 Singh et al, “Design and Optimization of Power Delivery Network for 3D Stacked Die Designs”, DesignCon 2011.
7Jairam et al, “A modeling approach for power integrity simulation in 3D-IC designs”, EETimes, April 2012.

Aveek Sarkar is vice president of product engineering & support at Apache Design Inc., a subsidiary of ANSYS.