The destiny of ports from design top that ultimately are driven from off-chip
Top level primary I/Os remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications are multifold for RTL and gate level simulations of them. This paper studies the “simulation-impacting” features of design top IOs and the effect of each feature on verification results.
Motivation and Contributions of Paper
The characteristics of the design top module being verified, the presence of library or Unified Power Format (UPF) attributes, semantic differences among UPF LRM revisions, and tool interpretations of these semantics can all have an impact on how corruption is modeled during power-aware verification; therefore, it is important to understand the role of each of these factors in order to mitigate any unintended effects. This paper presents empirical data based on a wide assortment of design top cases—showing how each of these variables influence contemporary EDA linting and verification tools.
The paper examines how UPF semantics related to port attributes have evolved over subsequent revisions and reviews specific questions faced by verification engineers relevant to how primary I/Os are modeled. It describes the scenarios tested and shares the results obtained when evaluating the tests with a contemporary low-power linter (LPLinter) and power-aware simulator (PASim).
The assignment of related supplies to top-level design top ports was investigated by providing four scenarios to power linting and power-aware simulator tools.
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