The three key “care-abouts” of choosing hardware-assisted verification.
Hardware-assisted verification and prototyping has become a mandatory requirement to allow design teams to gain confidence that a chip tape out can be initiated. The choice of the right hardware-accelerated engine is driven by its productivity, predictability, and use-model versatility, all impacting the key concern of users how to remove bugs. The XP Platform allows design teams to get to the point at which they are confident enough to tape out much faster, often shaving off two to four months off development cycles.
To view this white paper, click here.
30 facilities planned, including 10/7nm processes, but trade war and economic factors could slow progress.
Leaders of three R&D organizations, Imec, Leti and SRC, discuss the latest chip trends in AI, packaging and quantum computing.
Applied Materials’ VP looks at what’s next for semiconductor manufacturing and the impact of variation, new materials and different architectures.
What could make this memory type stand out from the next-gen memory crowd.
Researchers digging into ways around the von Neumann bottleneck.
Chips will cost more to design and manufacture even without pushing to the latest node, but that’s not the whole story.
This will go down as a good year for the semiconductor industry, where new markets and innovation were both necessary and rewarded.
Researchers digging into ways around the von Neumann bottleneck.
The term creates hope for some, fear for others, and confusion for all.
While CPUs continue to evolve, performance is no longer limited to a single processor type or process geometry.
Optimizing complex chips requires decisions about overall system architecture, and memory is a key variable.
Why data scrubbing and social issues could limit the speed of adoption and the usefulness of this technology.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply