Ready, Set, Go: Outrunning Moore’s Law With 3D-IC

By Anthony Mastroianni and Gordon Allan, Siemens EDA

3D ICs are an exciting and promising extension of heterogeneous advanced package technology into the third dimension. Although far from mainstream, 3D IC’s time is coming, as chiplet standardization efforts and supporting tool developments begin to make 3D IC practicable and profitable to more players – big and small – and products with smaller production runs.

3D IC enables companies to partition a design and integrate silicon IP at the most appropriate process node and process, providing low latency, high-bandwidth data movement, lower manufacturing costs, higher wafer yields, lower power consumption, and overall lower costs.

3D IC and chiplet-based design have the potential to accelerate the pace of semiconductor industry innovation and exceed the pace of Moore’s Law.

Fig. 1: In 3D IC design, several chiplets and an optional SoC are mounted and interconnected in a single package using high speed, high bandwidth chiplet-to-chiplet interfaces.

3D IC enables design teams to pack more functionality closer together and achieve higher levels of systems integration and performance in a small footprint faster, and in some cases more economically, than is possible in a traditional monolithic system on chip (SoC) implementation.

It’s no wonder there has been a great deal of growth and development in advanced heterogeneous packaging and 3D IC in the past several years.

But achieving the full potential of 3D IC requires cost-effective front-end design approaches that enable engineers and architects to evaluate the ramifications of different microarchitectures on physical size, power, performance, and cost of production, among other things.

Getting a head start on 3D IC

3D IC technology is applicable to multiple end-use markets for ICs, including mil-aero and space, high-performance computing, and consumer applications. This is one of many reasons why 3D IC is a technology that every front-end SoC design and verification team should become familiar with.

Making this paradigm shift to a heterogeneous integration design flow requires understanding several aspects of front-end 3D IC design and verification.

Packaging and partitioning are hard enough in a single-die SoC flow. Throwing heterogeneous integration and chiplets into the mix increases both design opportunities and complexity. So SoC architects need to evaluate and narrow down their architectural options even earlier in the process.

They need to know the steppingstones that get them there.

• Make architectural decisions around the packaging, partitioning, and reuse that affect the IC’s functional architecture.
• Understand how to build the interface connections: how to communicate from die-to-die and how to design that communication channel.
• Master interface verification: how to integrate and verify all those die-to-die connections using stan­dard protocols and memory interfaces.

Fig. 2: The 3D IC architectural planning workflow enables system and/or RTL designers to rapidly capture viable design architectures of heterogeneous integration design scenarios, including chiplet components — i.e., chip-to-chip (CTC) — and standard die-to-die (DTD) interfaces, using a library of generic connectivity IP models— i.e., CDKs.

Certain packaging and partitioning decisions should be made upfront from fixed criteria and experience. Other packaging and partitioning decisions will be decided during the architectural exploration and definition phase by evaluating several options and choosing one that meets the evolving requirements. Others will be deferred until the project has sufficient technical unknowns resolved to finalize these decisions.

Conclusion

The introduction of this new technology brings great opportunities previously not available to chip architects. It adds a lot more tools to the design toolkit and one more degree of architectural freedom that did not exist before. But with that comes a need to consider the impact on the whole design and manufacturing flows, and associated costs.

For a deeper introduction into the ways that predictive analytics will improve 3D IC design, the most cost-effective front-end 3D IC design approaches, and the groundwork that Siemens EDA is laying to deliver a more efficient, accessible, and profitable 3D IC design process, check out the new eBook Launching the full potential of 3D IC with front-end architectural planning from Siemens EDA.

With Siemens EDA as their partner, companies can begin designing tomorrow’s 3D IC devices today. Siemens is here to help our customers get ready, get set, and get going with their 3D IC heterogeneous package designs.

Gordon Allan is the Questa Verification IP Product Manager at Siemens EDA. Allan was one of the architects and developers of Accellera UVM and was responsible for the UVM Cookbook on Verification Academy. Prior to joining the EDA industry he gained over 18 years of SoC design and verification experience in lead engineer and senior consultant roles.