Custom memory IP optimization strategies.
The scaling benefits of Moore’s Law are challenging below 28nm. It is no longer a given that the cost per gate will go down at process nodes below 28nm, e.g., 20nm though 14nm and 7nm. Rising design and manufacturing costs are contributing factors to this trend.
Meanwhile, the competing trend of fewer but more complex system-on-chip (SoC) designs is reducing the knowledge base of many chip design teams. The reduction in knowledge means less IP availability at leading-edge process nodes. What can be done to mitigate these challenging trends?
Embedded memory continues to dominate the die area of many chips regardless of the process node. This suggests that significant benefit can be achieved by customizing the memory architectures of an SoC early on in the design process as part of the overall SoC optimization for power, performance and die area.
This white paper explores these challenges and highlights custom memory IP optimization strategies as a solution at 14/16nm nodes. These solutions have been implemented
in a variety of market segments, including machine learning, mobile tablets, multi-protocol switches, optical networks, carrier-grade Ethernet, gaming SoCs, digital TV (DTV) and medical devices. To read more, click here.
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