What we used to consider a design start will need to change. What do you call an SoC with extensive IP re-use?
For the past decade we have been hearing grim tales about the number of design starts shrinking and how that’s hurting EDA. While that makes for sensational headlines, reality is somewhat fuzzier and far less grim.
The big shift that’s underway isn’t so much a decline in design starts as a rise in SoCs. But SoCs are never really created from scratch. They’re a combination of commercial IP, re-used blocks from previous designs, and some new stuff thrown in. It’s hard to call that a design start. It’s not even certain that’s a derivative. And as we move into stacked die configurations over the next couple years, there will be even less that can be clearly defined.
This is hardly bad news for tools vendors. The increasing complexity of SoCs, versus ASICs or ASSPs, requires more tools and more sophistication on the part of the engineers using those tools. Emulation sales are on the rise. So is the number of classic EDA tools being sold, along with some non-classic ones. And with acquisitions by all of the big EDA players into adjacent markets, it’s not even clear what EDA really is anymore, or whether it should be called EDA.
These kinds of definitions were great for keeping investor interest in EDA in its stock-price boom years, but they will need to be revamped to keep pace with the changes in design. Semiconductor content continues to grow in everything from medical devices to automobiles and consumer electronics. It’s also more complicated than before, requiring more tools to develop, integrate and verify.
But how we define the process of creating semiconductors and how we break it down also can have a big impact on how much money is available for future development. This is an important job, and it’s one that needs to be done collaboratively by the business side of tools companies. It’s also one that needs to be done soon if the industry expects to realize its full potential.
—Ed Sperling
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