Reduced Power To The People!

Fifteen years ago, many of us involved in writing the design chapter of the ITRS (International Technology Roadmap for Semiconductors) already knew that power/energy consumption eventually would become a major problem for the industry’s growth. Engineers developing microprocessors (CPUs and DSPs) and graphics engines (GPUs) led the wave of predictions, because extrapolating known trend data showed that power would overtake timing as the primary concern of the future.

Most design teams kludged together in-house methodologies that awkwardly combined product marketing requirements, SPICE simulation data, spreadsheets, MatLab, ‘C’ code, and ad-hoc scripting to at least keep these growing trends in check. By the mid-2000s, a more automated and reliable approach was clearly required, paving the way for power intent formats like CPF and UPF that seven years later are now in widespread use. The gate and RTL-level techniques have become essential for almost any IC design, but we are nearing the limit of what can be achieved at these abstraction levels.

System architects have long known that 80% of a design’s optimization opportunity resides in the first 20% of the design flow, before too many implementation decisions have been fixed. Yet today’s power intent formats provide very little optimization beyond the RTL level. Today, as functional integration trends continue in a world filled with portable devices and huge server farms, the industry is ready for large-scale improvements that can only be delivered by moving up to the ESL and system levels of design abstraction. The word “system” in this context must necessarily include an understanding of the software running on the chipset, and the ability for co-optimization of hardware and software.

There are only two problems to solve. First, specifying ESL/architectural-level power intent requires an ability to efficiently model power behavior with clear semantics across both the modeling and intent format views. Second, bridging the gap with OS drivers, schedulers, and application software demands an ability to define the system-level use cases (profiles) that consume energy and correlate them back to the hardware being designed in terms of models and power intent.

A new standard is being introduced at this year’s DAC in San Francisco, supporting a novel approach called “Multi-Level Power Modeling” (MLPM), from Si2’s Low Power Coalition (LPC). This is the initial release of multiple enhancements anticipated in the coming years to offer the industry a common standard for modeling power at higher abstraction levels. In fact, as the name implies, the MLPM standard can model across transistor, cell, RTL, and ESL levels. Even better, one model can support all of these levels, reducing the effort of writing power models as the design is refined, and ensuring consistency of results.

In addition, Si2 and the members of the LPC are simultaneously addressing the software challenge, to involve system architects and software engineers in a WG to refine the practical requirements for communication across this traditional boundary. It is critical to have the proper domain experts evaluate incoming technology contribution(s), which can seed a new potential software-level standard. This standard must interact with MLPM, but also CPF and UPF standards, to enable co-optimization across all abstraction levels, including embedded software.

These new technologies are potentially “game changers” for the industry. But as significant as they may be, it is not sufficient without ensuring good coordination with both CPF and UPF, both of which continue to evolve. The IEEE Low Power Study Group just this week approved a PAR submitted by the LPC proposing a new system-level working group that would ensure close ties with IEEE-1801 as well as MLPM and any new software-oriented emerging standard.

If you are interested in this new work and plan to attend DAC, please take note of these presentations by LPC leading experts:

• Towards a Power Aware System-to-Silicon Design Flow; Jerry Frenkil, Si2
• Expanded Specifications for Advanced and System-Level Low Power; John Decker and Qi Wang, Cadence
• System Level Power Modeling Strategies: Bridging the HW and SW Worlds; Nagu Dhanwada, IBM

All of the events above are free of charge to DAC attendees. If you will not be at DAC, bookmark these links for later, where the delivered presentations will be available for download from Si2.

Also, don’t forget to mark your calendar for the annual Si2 Reception and Members meeting, Monday 4:30 to 6 p.m. in room 300 at the Moscone Center, featuring food and drinks, social networking, announcements from the CEO, and a special keynote talk by Leon Stok, Vice President, Electronic Design Automation Technologies, IBM and Chair of Si2’s Board of Directors (see http://si2.org/dac_2014/abstracts/leon_stok_abstract.php).