Reducing Cost And Mitigating Risk

Streamlined approaches are needed for more robust and reliable designs with better accuracy and predictability.


By Aveek Sarkar & Lawrence Williams
How will you design your next generation of products and keep pace with rapidly evolving market needs, while managing your margins? Many industries face these same design challenges. The speed of new product development—especially for meeting complex new design requirements—has never been more demanding. Historically, the rise in product development efforts has been incremental, but the bar is now much higher for producing new and compelling products with better performance at a lower cost.

While it is certainly challenging, the opportunities are wide open and provide manufacturers with the unique prospect of defining and differentiating their future products. Smart technologies enable countless new applications, driving a range of end-use market sectors and boosting sales. To meet these challenges manufacturers need flexible, yet accurate and predictive tools to design smart, low-cost, energy-efficient products and meet shrinking market windows.

It is possible to monitor and validate an entire design chain—from specification planning to system acceptance—by sharing models among teams and performing full systems simulations, which can be carried out by both IC and package/PCB designers within their own design flows. This approach allows for a package/system-aware IC design and an IC-aware
package/system design. As an example, a large electronics design organization may employ at least three design groups, including IC design, package design and printed circuit board (PCB) design. Typically, engineers in each of these disciplines work in isolation using independent design flows, but ultimately all design disciplines must deliver their parts to converge into a single working system. It is at this point a comprehensive multi-scale chip-package-system (CPS) flow and design sign-off methodology becomes a distinct advantage, giving developers the ability to simulate various physical phenomena across chips, packages and systems, including power optimization, signal integrity, electrostatic discharge (ESD), electromagnetic interference/electromagnetic compatibility (EMI/EMC), heat transfer, fluid dynamics and structural mechanics.



Traditional methodology (top) vs. chip-package-system flow (bottom) for sign-off.

With the increasing demand for smaller, lower-power portable devices, designing components in an isolated manner is no longer a valid approach. Engineers cannot work from the abstract of a schematic for individual components; they must consider the geometric description of the actual system to include all physical effects. This means being able to visualize the entire physical design, insert appropriate components (such as surface mount devices, connectors and ICs), and run frequency-domain and transient simulations with all the electromagnetic effects included.

However, these requirements are not just related to signal and power integrity. Systems designers also must account for RF and EMI effects, as most modern electronic devices contain both digital and RF. Engineers must perform comprehensive analyses to determine thermal, stress, shock and vibration effects. Using a flow that supports the design from layout, inclusion of signal integrity, power integrity, EMI, and 3D integration is key. It also must allow early system design exploration and prototyping to help designers understand the various components needed and to predict system behavior and cost very early in the design cycle.

There are a number of advantages to using a CPS methodology. For instance, it is possible to import a package/board layout, add components including ICs, and run circuit and system simulation from within that environment. This physical approach provides a more scalable and usable framework compared to the traditional schematic- or netlist-based approach. Engineers can populate the layout just as it is done in production and test. Of course, the schematic is there if needed to link to abstracted subsystems, drivers, receivers, etc. Once assembled, any arrangement of the chip + package + board can be inserted into a 3D design (such as a housing or full 3D product) for full 3D system analysis. Wireless antenna patterns, EMI, ESD and full-system integrity can be performed. So, 3D integration now happens during simulation, not later in the cycle when it is more difficult to make changes.

The CPS approach really benefits the entire electronics supply chain, especially IC suppliers and system integrators; providing a streamlined solution for achieving more robust and reliable designs with greater accuracy and predictability.

—Aveek Sarkar is vice president of engineering and support at Apache Design, Inc. (subsidiary of ANSYS); Lawrence Williams is director of product management at ANSYS Inc.


Aveek Sarkar

Aveek Sarkar


Lawrence Williams


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