Getting more functionality on the same die area using more and increasingly complex verification rules is getting more difficult. Here are some solutions.
Technology is both a blessing and a curse. The same shrinking of transistor size that has enabled chip designers to place significantly more functionality on the same die area is also responsible for the significant increases we have seen in the number and complexity of verification rules. It would be nice if we could use this phenomenon to our advantage, as an excuse for why our job of physical verification should take longer and why we should be given more time than we had for our previous project. As nice as that would be, this is not the case. Increasing competitive environments and the always present compulsion to get products out to market in a timely manner have not permitted such luxuries. Fortunately, despite conspiring forces to elongate this already difficult task, there is a light at the end of the tunnel (no, not a train coming the other direction), the Calibre suite of verification tools, specifically Calibre nmDRC, Calibre nmLVS and Calibre Incremental DRC.
To download this white paper, click here.
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