Reducing Schedule Slips With Automated Post-Route Verification Of SerDes High Speed Serial Links

Check a design’s serial links for protocol compliance before sending the board out to fabrication.


Most high-speed serial links don’t get verified once routing is complete because the process is time consuming and skill-intensive – and SI experts are in short supply. As a result, most serial channels are laid out according to rules, verified through manual inspection, and released to fabrication without thorough analysis. Unverified channels can result in lengthy (and hectic) prototype debugging, board spins, and schedule slips.

What’s needed is an automated post-route verification process that verifies all the channels in a design for detailed compliance with a SerDes protocol standard. Such a solution allows designers to find problems early in the layout process when they’re easier to correct, and release designs for fabrication with confidence, knowing all their serial channels have been verified.

The problem: lengthy post-route simulations and prototype debugging

If post-route verification of serial links is so important, why are so many PCB designs sent to prototype fab without full verification? Part of the issue is the prevalence of serial links in modern products. Everything is packed with serial links today – computers, phones, smart watches, cars – and the list goes on. There are a lot of designs, and a lot of links to verify. This leads into the second, and larger issue: there are simply not enough signal integrity experts to handle this much work. Signal integrity experts are often like artists – each one has their own style and approaches the task a bit differently. Much of what they do is based on detailed knowledge and experience, and it’s individual. There really isn’t anything like a signal integrity analysis assembly line – analysis flows aren’t standardized, and as a result, they’re not scalable. It’s like anything else with limited, highly skilled labor – too much work and too few people capable of practicing the art.

The result: companies must decide which sections of which designs merit an expert’s time and attention. Those projects get expert assistance, the others must do without or wait until an expert is available. Even on a single PCB layout, this can create costly bottlenecks. Companies can’t afford the resulting delays. Yet, they can’t afford to let random errors slip through undetected into prototypes in the lab, where finding, isolating, and debugging signal integrity problems takes longer, costs more money, and is notoriously difficult. So, what to do?

Until now, PCB design teams have typically followed one of four paths for analyzing their designs after layout.

  1. Send the board out for fabrication and hope for the best. The theory is that if manufacturer’s guidelines have been followed, the design should work. However, how can anyone be sure all the design guidelines have been followed?
  2. Visually inspect the layout to ensure design guidelines and best practices have been followed. This is certainly better than option 1, but visual inspection is tedious and time consuming, making it highly error prone. Design errors can be found this way, but it’s still a hit or miss proposition.
  3. Submit the design to an internal signal integrity expert for analysis. There are two requirements here: (a) there must actually be an internal signal integrity expert, and (b) the expert must have the time and tools available. Since there are too many designs and too few experts to go around, this is usually not the case. Yet even when an expert is available and their analysis shows problems that need to be corrected, the updated layout has to go back to the end of the queue, causing further delays.
  4. Send the layout to an external signal integrity consultant. This is a way to bypass an internal analysis queue or run analysis when no internal expert exists. This will get faster attention, presumably, but any design changes will cost both time and money because consultants won’t run that second set of simulations for free.

None of these are particularly great options. They either take on too much risk in order to get the design to fabrication earlier or impose lengthy delays in order to perform detailed signal integrity analysis. What’s needed is a fast, reliable way to validate designs after layout, without having to wait for a signal integrity expert or external consultant.

The solution: automated post-route verification

There are three essential steps in validating serial links before sending a design out to fabrication:

  1. Electromagnetic modeling
  2. Analysis
  3. Results processing

All three of these flows have traditionally been largely manual efforts, consisting of multiple steps, and requiring SI experts. If we combine the three steps into a process chart for a traditional flow, it looks something like what is shown in figure 1.

Fig. 1: Process chart for a traditional compliance analysis flow.

The red arrows indicate parts of the flow where data must be examined for accuracy and the parts of the process repeated if things need to be adjusted. Again, this diagram shows a compliance analysis flow using a traditional methodology. An IBIS-AMI flow would have fewer elements, but the simulation step itself would be more complex.

HyperLynx from Siemens DISW makes it possible to validate all of a design’s serial links for protocol compliance before sending the board out to fabrication—without a lengthy and highly skilled and labor-intensive process.

HyperLynx can automate the entire post-layout verification process because Siemens provides all the necessary EDA tools in the HyperLynx family, integrated with a single, automated workflow. This includes the automated identification of critical areas that need to be modeled with a full-wave solver, assembly of the full channel model from individual pieces once everything has been solved, analysis of the resulting channel models for compliance (analysis), and formatting the results to show which channels passed, which channels failed, and by how much (results processing). The HyperLynx process for post-route serial channel protocol verification looks like what is shown in figure 2.

Fig. 2: HyperLynx process for post-route serial channel protocol verification.

This automated process means all the channels in a large system design can be modeled and analyzed. The electromagnetic modeling process can be accelerated by running multiple solvers in parallel, so users can control the run time versus required-resource tradeoffs based on their project needs. Most importantly, HyperLynx tells you exactly what you want to know: which channels pass, which channels fail and by how much – all in a detailed report that includes frequency and time domain plots and eye diagrams.

Everything you need to know, in one place, organized and cross-referenced. That means you can analyze all the channels in your design for protocol compliance – automatically, overnight. It’s fast and easy enough to analyze your channels to find problems while the design is still in layout. So you don’t have to wait until layout is complete and rework is more expensive.

Fig. 3: HyperLynx detailed reports.

For a more detailed review of why complete post-route analysis is considered too time-consuming and too expensive and how the automated compliance analysis flow using HyperLynx overcomes the limitations of these traditional post-route analysis methods, please download the whitepaper Automated Compliance Analysis of Serial Links Reduces Schedule Risk. The paper explains how design teams can verify all of the serial links in their designs overnight, improving design performance and reducing schedule risk—and help you deliver tomorrow’s high-speed designs today.


Todd Bermensolo says:

Excellent write-up Todd Westerhoff! Even if you do have a signal integrity expert available, this type of automation would make simulation analysis more efficient and make the experts more productive.

I would especially love to see this type of automation analysis to also include PCB manufacturing variations. Many times the dimensions in the layout are different to what is finally built when PCB manufacturers adjust to meet impedance and insertion loss targets. The nominal looks okay, but specification limit cases fail (i.e. high/low impedance, high/loss loss, etc).

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