Rethinking Low Power Verification: LP + CDC Verification

In my last posting, we discussed some of the barriers that companies face in seeking to meet their low power verification objectives, and how the complete and integrated technologies in Synopsys’ new Verification Compiler product can help. This time, I’d like to introduce a relevant example of how unified technology solutions can help address complex design interactions in low power verification, and I’ll also introduce Namit Gupta, our corporate applications engineering expert on CDC verification. Namit will talk about why it’s imperative to perform static CDC verification within the context of low power implementation and verification flows.

LP-Aware CDC Checks – Namit Gupta, CAE Verification Group
Every low power SoC design will require extensive CDC verification, and this must be done in conjunction with low power verification. Clock crossings on paths inferred from UPF low power intent don’t appear in the design RTL, and it is far too late in the design process to verify the PG netlist post place and route. It is imperative that CDC checking uses the same view of the design as low power static checking (such as with Synopsys’ VC LP tool), and similarly, used early in the design process. This unified methodology is the only way to really enable design teams to fully verify low power intent and implementation, and remove LP/CDC bugs which are easy to find and fix early in the flow, from the simulation flow, where these become much harder to detect and debug.

Example – Isolation Control Strategy

Assume Figure 1. below is a RTL representation of an example design with two clocks (C1 and C2), and some sort of power management controller clocked on C2:

Figure 1.

The user specifies the following isolation strategy in the UPF power intent:

set_isolation outputs_only

-domain A

-isolation_power_net VDD_A

-clamp_value 0

-applies_to outputs

set_isolation_control outputs_only

-domain A

-isolation_signal ISO

-isolation_sense low

-location self

Then the resulting post-synthesis netlist will also include the logic in orange inferred from the UPF (Figure 2, below):

Figure 2

The path from ISO > Out1 > Flop 3 marked by the red dashed line is a CDC path, and cannot be detected solely from the RTL. This type of CDC path can be very widespread depending on design styles, so it’s imperative that these paths are identified and verified early in the design cycle, prior to synthesis. Similarly, CDC violations may arise from other low power design techniques, and all of these require integrated LP and CDC static checking to enable comprehensive checking.

The only way these LP CDC paths can be checked at RTL is if the CDC tool can infer the power network from the UPF description. Because Synopsys’ VC CDC static checking tool is built on the same advanced static technology base as our VC LP low power static checker, we are able to check the CDC paths on exactly the same design, which includes the CDC paths on the inferred power network. VC LP’s and VC CDC’s RTL and UPF hardware inference engines are also common across all Synopsys verification tools, and this guarantees excellent correlation to Design Compiler post-synthesis netlists, as well as RTL simulation with VCS Native Low Power.  This allows implementation engineers to quickly, easily and comprehensively verify their low power design intent, and uniquely bridges the implementation and verification worlds.