Enabling a DFP methodology requires designers to begin early in the design process at RTL.
Commercial power analysis tools have been available now for over 10 years, operating at the gate and transistor level of abstraction. For analog, mixed-signal, and custom designs, transistor-level tools are utilized as both design and verification tools, meaning that they help designers analyzing power and serve as the final ‘sign-off’ to ensure that power specifications are met. For standard-cell ASIC and SoC designs, gate-level and transistor-level power analysis tools can only be used as the final verification tools because they are used late in the overall design flow. This white paper presents a DFP methodology, beginning early in the design process at the register transfer level (RTL).
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