Enabling a DFP methodology requires designers to begin early in the design process at RTL.
Commercial power analysis tools have been available now for over 10 years, operating at the gate and transistor level of abstraction. For analog, mixed-signal, and custom designs, transistor-level tools are utilized as both design and verification tools, meaning that they help designers analyzing power and serve as the final ‘sign-off’ to ensure that power specifications are met. For standard-cell ASIC and SoC designs, gate-level and transistor-level power analysis tools can only be used as the final verification tools because they are used late in the overall design flow. This white paper presents a DFP methodology, beginning early in the design process at the register transfer level (RTL).
To read more, click here.
Rising costs and gaps in equipment emerge as technology scales; new tools under development.
Explosion of data is forcing significant changes in where processing is done.
Is it possible to reduce the power consumed by memory by 50%? Yes, but it requires work in the memory and at the architecture level.
2019 will be a year of change for the semiconductor industry as new fields drive technological advancements.
This new communications standard could transform architectural decisions across the industry, but not right away and not necessarily in obvious ways.
What hoops will designers have to jump through to avoid concurrency bugs?
Why managing power is becoming more difficult, more critical, and much more expensive.
Analog circuitry stopped following Moore’s Law a long time ago, but that hasn’t always helped.
Is it possible to reduce the power consumed by memory by 50%? Yes, but it requires work in the memory and at the architecture level.
Can mixed-signal architectures boost artificial intelligence performance using less power?
When going to a smaller node is no longer an option, how do you get better power performance? Several techniques are possible.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply