RTL Power Estimation

By Luke Lang
A few months ago, I wrote about power estimation—finding the worst-case toggle rate to determine the worst-case power. This has been used very successfully by many designers to get an accurate estimation and analysis of power dissipation. These designers also are using the worst-case toggle rate to optimize power grid and meet dynamic IR drop requirements. With these power estimation capabilities, one might think that the designers would be very happy and satisfied. But they are not, because many of these designs are not meeting the power requirement.

It reminds me of the movie. “Back to the Future, Part II.” You get to see the future, but it is not what you wanted. In the movie, Marty McFly goes back to 1955 to change the future. Unfortunately, we don’t have a DeLorean with a flux capacitor, and often the designer finds out too late that the power target is not met.

Usually, the problem occurs when power estimation is first done after synthesis. The designer is often surprised by the high power estimate. At the synthesis stage of the design cycle, many features and architectures have been decided. It might be possible to perform some power optimization, but very often, timing optimization is needed resulting in even more power dissipation. There is simply not enough time to re-architect and still meet the overall project schedule.

We certainly need accurate power estimation, but we also need early power estimation. We need to compare different power architectures and evaluate alternative micro architectures. We need to know what kind of design we have and where to optimize for power. For example, if the datapath dissipates 15% of the power, that is probably not the first place to look for power reduction. On the other hand, if the clock tree dissipates 35% of the power, that is probably a great place to start looking for power reduction.

Some designers do perform RTL power estimation, but they get grossly inaccurate results. The problem is that most RTL power estimation tools are not timing or synthesis aware. Given an RTL design and running it at 10 MHz, 100 MHz, or 1 GHz, we certainly don’t expect that power per MHz is going to be the same at all clock frequencies. Without some synthesis awareness, the power estimator would not have any idea about critical path, gate structure, and load capacitance. These are all very important parameters that have a huge impact on power estimation. For example, at 10 MHz, we can use a ripple adder. But at 1 GHz, we need a much faster adder. The difference in power dissipation is tremendous.

Timing and synthesis awareness enable fairly accurate power estimation early in the design cycle. We can analyze and compare different micro architectures. We can determine how various low-power design techniques can impact power. We can even evaluate whether a particular function or feature can be added to the chip from a power point of view. We can also fine-tune RTL code to minimize power. Most importantly, we can do all of these optimizations without significant impact to schedule.

It is well known that the architectural decisions made at the beginning of the design cycle have the greatest impact on power. Late in the design cycle, there is very little that we can do to reduce power. If you are very concerned about power, make sure that you are estimating power early and accurately.

–Luke Lang is a senior product engineering manager at Cadence.