What it is, why you need it and how Atrenta can help
We all know that hierarchy created for logic design must often be adjusted to map to a physical implementation. Logic hierarchy is typically constrained by non-implementation factors, especially organization of teams working on different components and use of legacy or 3rd party IP. Physical hierarchy, on the other hand, must partition the logic to fit detailed implementation tool capacity limits and to optimize for timing and area. These competing needs are unlikely to align by chance and forcing alignment at design start is not an option open to most.
For the implementation cycle, this problem is solved. All physical design tools provide methods to restructure logic. So, what’s the issue? As always, technology and needs have advanced in ways that require at least part of this solution to be re-thought from the ground up.
Deep sub-micron design is driving a need for multiple physical trials during the evolution of the RTL. This forces implementation teams to restructure multiple times with scripts that must be re-designed for every re-map, slowing down the process and limiting the number of possible trials.
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