Scaling In The AI Era: The Role Of PCI Express 7.0 Switches In Next-Gen Data Centers

As artificial intelligence (AI) workloads continue to scale in complexity and volume, the infrastructure that supports them must evolve just as rapidly. At the heart of this transformation lies PCI Express 7.0 (PCIe 7.0), a next-generation interconnect standard that is redefining how data moves within high-performance computing (HPC) and AI-driven data centers.

PCIe 7.0 doubles the raw bit rate of its predecessor to 128 GT/s and delivers up to 512 GB/s of bi-directional bandwidth over a 16-lane configuration. This leap is not just about speed—it’s about enabling the seamless flow of data between thousands of AI accelerators, GPUs, and memory subsystems. In modern AI training environments, where large language models (LLMs) and deep learning frameworks demand massive parallelism, PCIe 7.0 aims to ensure that compute resources are not bottlenecked by interconnect limitations.

Further, as data centers shift toward disaggregated architectures—where compute, memory, and storage are decoupled and dynamically composed— PCIe becomes a foundational interconnect technology. In these architectures, switches will be key building blocks for implementing high-speed interconnects between computing assets with the flexibility to support composability. Furthermore, the use of standalone switches will be supplemented with embedded switches integrated together within complex interconnect chips such as SmartNICs (Smart Network Interface Cards).

SmartNICs are architected to perform network offload management, saving as much as 20% of CPU cycles. Including an embedded switch as part of a SmartNIC provides a means for one or multiple servers to access more endpoint resources, such as SSDs, GPUs, etc., through the lower latency offered by PCIe interconnect technology, while simultaneously providing access to the Ethernet network via a NIC interface.

Given the speed at which PCIe technology is evolving to support the needs of advanced workloads like AI, PCIe 7.0-enabled devices will be deployed in heterogeneous networks alongside existing PCIe 6.x, 5.x, and even 4.x generation devices. As such, backward compatibility from PCIe 7.0 to previous generations will be a must.

PCIe 6.0 represented one of the biggest evolutions of the standard in its history. PCIe 6.0 adopted PAM4 signaling (vs. NRZ of previous generations) and fixed length packets (FLITs) vs. variable length packets. PCIe 7.0 builds on these same innovations. An ideal PCIe 7.0 switch, given the heterogeneous environment described above, would provide ultra-low latency, high throughput, backward compatibility and FLIT-to-non-FLIT conversion to support next-gen and legacy devices.

As a leader in PCIe IP, Rambus offers state-of-the-art PCIe 7.0 switch IP with all the above characteristics and these features:

• Support of up to 31 downstream ports and two upstream ports, enabling flexible topologies that can scale with the demands of AI clusters
• Non-blocking multi-stage crossbar architecture for efficient data routing
• Configurable egress buffers for non-blocking output

By enabling scalable, high-bandwidth, and low-latency interconnects, PCIe 7.0 switches will be key to meeting the demands of AI at scale. As the industry moves toward more distributed and intelligent infrastructure, PCIe 7.0 will be a cornerstone technology supporting that drive forward. Rambus, as a trusted supplier of PCIe switch, controller and retimer IP, helps chip makers achieve the promise of PCIe 7.0 performance in their state-of-the-art SoC designs.

Related links

• Rambus PCIe 7.0 Switch IP
• Rambus PCIe IP Products