Self-Service Comparisons Come To SoC Design

Under the guise of enabling self-service comparison of its compilable memories and providing self-service online quoting of TSMC technology, semiconductor design and manufacturing services provider eSilicon Corp. detailed the latest evolution of its business model—and one that could have interesting implications for the IP and memory markets.

This move reflects the changing dynamics of customer engagements, which puts demands on services and technology providers to deliver more nimbly, as well as the need to understand how IP and other components will be used, how they will be connected, and the context of all of these parts. Selling parts in context has been a big push for IP vendors, which are pulling various IP components together into partial or full subsystems or even platforms. Being able to swap components in and out of that mix and judge how they will perform compared with other possible choices is the next step.

This trend has been building momentum for at least the past couple of years. Companies such as Synopsys, ARM, Cadence and Imagination all have been integrating different pieces of IP and providing well-characterized blocks and subsystems, and the stated goal by all of them is to add more of those pieces together where it makes sense. eSilicon’s approach is similar, although it approaches the goal as a memory maker and integrator of other IP. And while all of this is useful in SoC design, it will become particularly important in the era of 2.5D and 3D stacked die, where the ability to put pieces together more quickly and understand their idiosyncrasies will be critical.

Building on its eSilicon Access product management system, originally launched in 2000, and bolstered by a multi-project wafer quoting utility unveiled last October, the company is detailing today two more capabilities in the vein of enabling self-service access to its services. The first is IP MarketPlace, which allows interactive exploration of eSilicon-designed compilable memories to determine the best power, performance or area (PPA) fit for a particular SoC design. The user can download Microsoft Excel summaries of PPA performance of the chosen memories for further analysis, along with datasheets and IP silicon reports. IP MarketPlace is still in development with plans for use this fall. While not marketed as such, IP MarketPlace is a cloud-based application – the likes of which is specific enough to stand a fighting chance in the EDA industry, which has been mulling over the cloud opportunity for some time. The ability to compare IP online is not new, but Mike Gianfagna, eSilicon’s VP of marketing says this differs from Design&Reuse, ChipEstimate and Avnet Express in that different memories can be configured as well as compared which gives the user more flexibility in the tradeoff process.

The next part of eSilicon’s story today is significant. Touted as an expansion of its online automation suite, the company is adding what it refers to as a GDSII portal for quick, automated quoting for TSMC foundry technologies – with the possibility to add additional foundry portals in the future.

It builds on eSilicon’s instant online quoting system for multi-project wafer (MPW) shuttle services and allows users to fully specify the manufacturing process requirements for submission of a GDSII design to TSMC for manufacturing.

The user specifies the required manufacturing process information through a series of menus, as well as the requirements for packaging, testing and delivery. An executable quotation from eSilicon is provided that includes non-recurring engineering (NRE) pricing and unit pricing for the system-on-chip (SoC) device. The resulting quote levels the playing field for smaller customers, giving them what would seem to be the peace of mind to know the quote is fair and not based on subjective criteria.

What is particularly intriguing about this is the variety of potential use cases. While someone with a completed design can use the system when they are shopping for a manufacturer, a big potential lies in the system’s ability to show design teams up front the tangible, monetary impact of their packaging options, which must be considered early on, as well as the power and performance penalties of one choice versus another. Having more data about the impact of the packaging decision can also guide the design team in optimizing the design for the specific packaging choice.

eSilicon said the GDSII portal will be available for general customer use late next month and the company will be demo-ing both technologies at the upcoming Design Automation Conference.

*Edited to reflect the fact that only TSMC has committed to the GDSII portal at this time. The author apologizes for the mistake.