Shift Left In DFT Design

The semiconductor industry continues to face numerous challenges as designs approach reticle limits, process nodes evolve and engineering resources become increasingly stretched. It is essential to maintain high productivity and quality throughout the design flow. This keeps projects on schedule, within budget, and ensures they remain high-quality, reliable, yield well and perform as intended.

Shifting left for DFT-related (Design for Test) tasks enables engineers to identify and address design issues earlier. This reduces the impact of DFT on the critical path during the chip design process. Adopting a shift-left strategy enhances productivity and product quality by moving certain activities to earlier stages of the design process. This approach allows engineers to gain insights into their designs earlier, reducing the number of iterations required and lessening the demands on engineering resources, ultimately improving overall design quality.

Siemens EDA supports the semiconductor industry in addressing current market demands by developing IC test products that allow designers to meet power, performance, area (PPA) and testability objectives. The goal is to reduce design effort while maximizing cost-effectiveness, yield and resource utilization. Each phase of the design flow offers unique “shift-left” capabilities to support this effort.

A significant trend in IC design is the adoption of a “shift-left” strategy. This method focuses on identifying and resolving issues earlier in the RTL-to-signoff process, using data to address problems more promptly and effectively shifting the problem-solving phase to an earlier point in the timeline. The practice of shifting left with DFT should include design analysis, test insertion and verification of the DFT structures inserted in the design. Shifting left should improve productivity through the reading and writing of RTL and the direct insertion of DFT logic into the design RTL for synthesis in any tool.

The introduction of Tessent RTL Pro software has enhanced shift-left capabilities by allowing the integration of additional test IP directly at the Register Transfer Level (RTL). With Tessent RTL Pro, engineers can analyze and incorporate testability-related structures, such as core wrapper cells, x-bounding logic and test points directly into the RTL. A common design trend is to follow this RTL insertion of DFT structures with quick synthesis. This is then followed by scan and Automatic Test Pattern Generation (ATPG), enabling the identification of coverage and pattern count outliers in a fraction of the time compared to traditional synthesis methods (figure 1).

Fig. 1: Quick synthesis shortens the time to learning and allows the earlier identification of test outliers. Engineers can work on debugging test coverage and pattern count sooner rather than waiting for synthesis and optimization to complete.

There are benefits to incorporating test logic into the RTL:

1. Synthesis tools can optimize the design while considering the impact of test logic on timing and layout, and
2. Design rule checks (DRCs) are performed earlier in the development process, meaning that clock, set and reset controllability for scan can be validated earlier.

Tessent conducts comprehensive DRCs based on the specific DFT logic selected for insertion. This capability enables the software to analyze the design intelligently, focusing solely on the paths that require sensitization for the chosen DFT logic. These design rule checks ensure that critical signals reach their intended destination in the appropriate test mode. Furthermore, Tessent software analyzes the design downstream, identifying the inserted Tessent test logic. This streamlines the process and saves designers time by eliminating the need to identify these logic structures manually.

The RTL produced by Tessent solutions retains a familiar appearance compared to the input RTL, making it easy to visually identify modifications made to the design files. Once all test logic (except for scan) is integrated into the RTL, synthesis can optimize for PPA and testability, using the nearly complete design.

Inserting test points at the RTL stage is crucial for meeting ISO 26262 standards of functional safety and automotive designs. This approach enhances the implementation of VersaPoint and OST test points, ensuring compatibility with all downstream synthesis design flows. Moreover, the capability to analyze and insert essential DFT logic—such as EDT (Embedded Diagnostic Test), Tessent SSN (Streaming Scan Network) and BIST (Built-In Self-Test) logic, including wrapper cells and x-bounding logic—allows customers to further their shift-left initiatives by significantly improving the testability of their RTL designs.

Tessent DFT solutions facilitate shift-left design workflows, providing designers with the necessary tools to reduce turnaround times, gain early insights into their circuits, and identify and resolve issues more efficiently. With the launch of Tessent RTL Pro, Tessent continues to offer the industry’s most advanced DFT solutions tailored for modern design flows.

To learn more about shifting left in DFT, refer to the white paper on this topic.