Simplify DFT For Advanced SoCs

The purpose of electronic design automation (EDA) software is to solve SoC design problems and simplify the entire process. For design for test (DFT), this means aiming to streamline the DFT development for today’s large and complex designs. The technologies and methods developed through partnerships between EDA suppliers, foundries, and semiconductor companies should effectively reduce risk, improve time-to-market, and provide a more predictable and reliable DFT solution.

Leonardo DaVinci said that “Simplicity is the ultimate sophistication.” Semiconductor design is a very complex process that takes hundreds or thousands of process steps. Each step introduces risk; every company wants to reduce that risk and get from concept to hardware as predictably as possible without unexpected delays and costs. Automation is the tried-and-true method, but not all automation keeps up with the ever-increasing complexity of semiconductor design.

DFT designers, like all engineers, have to continuously tune their process to find the sweet spot of test quality, time, DFT effort, and cost. When designs get more complex and the software doesn’t adequately simplify the problem, the whole project starts to look like a Rube Goldberg machine—overly complex and impractical. For example, say your DFT flow has 100 steps, each has a 99% success rate. That’s .99¹⁰⁰ = 36% success rate. We can see how extraordinary the success of a very complex project is in the recently deployed James Webb telescope. With 344 points of failure just within the deployment, each step had to have a significantly higher than 99% success rate.

At some point, the complexity of SoC designs outpaces the incumbent automation solutions and will put new projects at risk. This is when the team has to ask how reliable and repeatable their process is, then change it as needed.

EDA strategy

The industry challenges of technology scaling, design scaling, and system scaling drive the software strategy within EDA providers like Siemens. For DFT, that translates to creating specific technologies and flows to address each of these challenges (figure 1).

Fig. 1: The three big industry challenges are addressed with various DFT and test software, IP, flows, and methodologies.

DFT automation for technology scaling requires higher fidelity and precision, better statistical diagnosis, and defect-oriented test. For design scaling challenges including 2.5D and 3D packaging issues, the focus is on shifting left; do the work earlier in the flow, use a true hierarchical flow and bus-based packetized test delivery. For system scaling challenges, solutions include newer built-in self-test, in-system test, Embedded Analytics, and lifecycle management.

Success with automation

When you have a large, complex problem, the solution could be to introduce more automation, more steps, more iterations and maybe add some artificial intelligence algorithms to process complex analyses and tradeoffs.

But sometimes the better solution is to remove complexity. Hierarchical DFT does this. A plug-and-play solution makes core-level DFT independent from the SoC-level embedding. Packetized test data makes the core-level test independent from the top-level IOs. Both of these technologies greatly simplify the problem, removing iteration and optimization steps entirely. Failure diagnosis, likewise, works with the hierarchical layout to simplify the process of identifying and locating faults.

Design teams need to think of DFT from the SoC level and ensure the DFT architecture is good. There are a few newer technologies that streamline and simplify any DFT project—IJTAG, Streaming Scan Network (packetized test delivery), on-chip compare in cores, and hierarchical DFT. Many of these solutions are embedded in existing EDA software and others are new, but each has demonstrated significant advantages in real designs. To hear industry DFT experts describe their experiences with some of these newer technologies visit our 2021 International Test Conference videos page.