tag: hierarchical DFT

Advanced DFT And Silicon Bring-Up For AI Chips
By Lee Harrison - 07 Dec, 2023 - Comments: 0

The AI market is growing quickly, spurring an insatiable demand for powerful AI accelerators. AI chip makers are pressed with aggressive time-to-market goals and need the tools to help them get their chips into the hands of customers as quickly as possible. IC test and silicon bring-up are tasks that can affect both the quality and the time-to-market of AI chips. Different companies are usin... » read more

Testing The Stack: DFT Is Ready For 3D Devices
By Martin Keim - 08 Sep, 2022 - Comments: 0

When existing advanced 2D designs already push the limits of design-for-test (DFT) tools, what hope do developers have of managing DFT for 3D devices? Can anyone afford the tool run time, on-chip area demand, pattern count, and test time? The answer, from an array of experts, is yes, there is a path to a scalable, affordable, and comprehensive DFT solution for 3D ICs. Well-covered strategies... » read more

Simplify DFT For Advanced SoCs
By Ron Press - 08 Feb, 2022 - Comments: 0

The purpose of electronic design automation (EDA) software is to solve SoC design problems and simplify the entire process. For design for test (DFT), this means aiming to streamline the DFT development for today’s large and complex designs. The technologies and methods developed through partnerships between EDA suppliers, foundries, and semiconductor companies should effectively reduce risk,... » read more

The Single Best DFT Move You Can Make
By Jay Jahangiri - 08 Oct, 2019 - Comments: 0

A proven method to simplify a complex problem is to break it into smaller chunks. In the case of today’s large, complex SoCs, this means using hierarchical methods to design the blocks, then combine the results at the top level. While this sounds obvious, it hasn’t always been practical or technologically feasible to perform some tasks, like DFT, at the block level and translate that work s... » read more

Hierarchical DFT: Proven Divide-And-Conquer Solution Accelerates DFT Implementation And Reduces Test Costs
By Mentor, a Siemens Business - 07 Oct, 2019 - Comments: 0

Implementation of the most challenging DFT tasks is greatly simplified by the proven and widely-adopted automation available in Tessent products. This whitepaper describes the basic components of an RTL-based hierarchical DFT methodology, the benefits that it provides, and the tool automation that is available through Mentor’s Tessent products. The focus is on the techniques and automation of... » read more

Hierarchical DFT On A Flat Layout Design
By Vidya Neerkundar - 06 Aug, 2019 - Comments: 0

The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules.  Hierarchical DFT divides the design into smaller pieces, creates test structures and patterns at the core level, then retargets the core patterns to the chip level. But, if you need to perform the physical place and route on the full flat design, can you still take a... » read more

Smart Plug-And-Play DFT For Arm Cores
By Ron Press - 11 Jun, 2019 - Comments: 0

Modern SoCs are experiencing continued growth in capabilities and design sizes with more and more subsystem IPs being implemented. These large, complex, multi-core SoCs need strategies for DFT and ATPG that effectively reduce DFT effort, minimize ATPG runtime, and still achieve the target test coverage. Hierarchical DFT enables designing and testing of these designs in a systematic and repeatab... » read more

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy