Hierarchical DFT On A Flat Layout Design

If you need to perform full-flat physical implementation, can you still take advantage of hierarchical DFT methods?


The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules.  Hierarchical DFT divides the design into smaller pieces, creates test structures and patterns at the core level, then retargets the core patterns to the chip level. But, if you need to perform the physical place and route on the full flat design, can you still take advantage of hierarchical DFT methods?

If the place and route is done on the full chip-level design (as opposed to hierarchically), the DFT work would traditionally also be performed once on the full, flat design. However, for large designs with many memory instances, chip-level DFT is likely to be too time consuming and inefficient. ON Semiconductor has answered that question by using hierarchical memory BIST insertion, but still performing physical implementation on the flat layout.

ON Semiconductor had a simple goal: reduce the time it took to insert and synthesize memory BIST for a multi-million gate-level netlist with 300 memory instances. Physical implementation had to be done on the full, flat layout, but they needed to insert and implement DFT more quickly. The time required to insert memory BIST and perform synthesis of the memory BIST hardware typically took ON Semiconductor about 9 hours (Fig 1). The long run times prevented the engineers from performing what-if scenarios to optimize the outcome.

Fig. 1. Memory BIST insertion for the test case design, without using hierarchy.

While memory BIST seems straightforward, the quality can vary significantly depending on a number of factors. Considerations in memory BIST include:

  • How are the memories to be grouped? This relies on input from the physical floor-planning stage of the design.
  • Which memories belong to which clock domain? This helps in determining the number of independent controllers needed.
  • What are the power dissipation requirements? This determines how many memories can be tested in parallel.
  • Do any memories need specific algorithms to be programmed during memory BIST test?
  • Which memories can share repair?
  • What is the required diagnostic resolution?

Based on analysis of the floor planning information by the memory BIST tool, ON Semiconductor divided the multi-million gate-level design into 13 submodules (not physical hierarchical regions) and then performed memory BIST insertion and synthesis on these 13 sub modules in parallel.

Hierarchical DFT techniques, for BIST as well as scan, use the idea of divide-and-conquer to reduce the time it takes to perform any given task. All the test insertion is done on cores or blocks separately (Fig 2). This allows teams to parallelize the work effort and improve productivity.

Fig. 2. Hierarchical architecture with scan, embedded compression, and wrapper chains in each block and at the top level.

The time ON Semiconductor needed to perform both memory BIST insertion and synthesis once the design was divided into submodules was drastically reduced from 9 hours to about 1.5 hours. This windfall allowed the team to perform multiple iterations within the same day and also finish other tasks that need to be performed, including running what-if scenarios to optimize the results.

The reduction in the time it took to insert and synthesize memory BIST comes from dividing up the flat design into virtual hierarchical blocks, which allows DFT insertion and synthesis to be executed in parallel on smaller design components. This productivity advantage is a consequence from the applied hierarchical principle and as such would apply to any DFT insertion, not just to the memory BIST example used here.

After hierarchical memory BIST insertion and synthesis, the chip-level DFT work included the use of the IJTAG (IEEE 1687 standard) and Tessent MemoryBIST to help generate memory BIST patterns not just for testbench simulation but also for generating WGL/STIL patterns that can be supplied to the tester.

Design teams are always looking for new ways to perform the more time-consuming DFT tasks more efficiently as the size and complexity of the design increase. Hierarchical DFT used to be user managed with multiple scripts and error-prone without automation. Out of necessity, it has become the target of automation and standards (like IEEE 1687) and is now quite mature. Adopting a hierarchical DFT methodology is proving to be a winning strategy for many semiconductor companies.

ON Semiconductor operates in a highly competitive IC market, so any easy-to-adopt technique that improves the design time, lowers cost, or improves quality can infer a competitive edge. For DFT engineers, an area ripe for improvement in runtime and quality on huge designs is in DFT insertion and synthesis. Hierarchical DFT allows the DFT work to be performed in concurrent parallel insertion and synthesis runs. As the ON Semiconductor case study shows, hierarchical memory BIST works for even for designs that will go through a flat place and route flow. The hierarchical DFT flow helped ON Semiconductor to attain the desired results with improved productivity.

For the full case study, download our whitepaper “ON Semiconductor Reduces Memory BIST Insertion Time by 6X with Tessent Hierarchical Flow.”

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