Simplifying HW/SW Co-Verification With PSS Led UVM And C Tests

By Todd Burkholder, Wael Abdelaziz Mahmoud, Tom Fitzpatrick, Vishal Baskar, and Mohamed Nafea

The complexity of system on chips (SoCs) continues to grow rapidly with the integration of more functionality onto a single chip. As a result, traditional verification methodologies struggle to keep pace with the growing complexities, leading to longer development cycles and increased risk of design errors. In response to this challenge, hardware and software co-verification emerges as a pivotal technique in validating SoC designs.

However, there is much testing that needs to be done at the block- and subsystem-level before software-driven system-level testing can begin. Traditionally, this early testing is done in simulation using the Universal Verification Methodology (UVM) to create a set of modular reusable verification components assembled into “testbenches” (UVM environments), including stimulus sequences to exercise specific transactions across the different interfaces of the device-under-test (DUT). When the full SoC design is assembled, it usually includes an embedded processor and requires software, usually written in C, to exercise the same functionality that was previously modeled as UVM transactions driven by an agent executing a sequence. This need to duplicate the verification implementation, first in UVM and then later in C, is a substantial bottleneck that negatively impacts the verification productivity of many projects.

The Portable Test and Stimulus Standard (PSS) from Accellera was architected specifically to address this need to reuse verification intent throughout a project across multiple, possibly heterogeneous, implementations. By definition, a PSS test defines a set of actions that represent the verification behaviors required to exercise desired functionality of the DUT. These actions themselves can be defined at multiple levels of abstraction, from basic bus read/write operations to higher-level actions, such as direct memory access (DMA) transfers, message passing, or other behaviors. An action that may be driven by a UVM agent at the block level may easily represent a C-level function that may be called from a software driver running in the embedded processor at the SoC level.

However, we need a way to cross the boundaries between UVM-based tests and C-tests in an organized and seamless way. In this article, we introduce the combination of the PSS, UVM, and C++ wherein it offers superior advantages for HW/SW co-verification in SoC designs. PSS enables the creation of reusable and adaptable verification scenarios across multiple platforms, enhancing productivity and reducing verification time. UVM provides a robust and standardized framework for creating modular and reusable verification components, promoting consistency, and reducing duplication of effort. The use of C++ in conjunction with PSS and UVM allows for high-performance and flexible testbench development, leveraging object-oriented programming to manage complexity and improve maintainability.

The proposed methodology can be summarized in the following steps (figure 1):

1. Explore testbench environment and develop PSS model
2. Debug PSS (abstract and solved) models using Siemens’ PSS-compliant user interface debugger tool
3. Implement the realization model by adding the contents of the actions’ exec blocks for both C and UVM tests
4. Solve PSS module and generate corresponding tests (C and UVM) using Siemens’ PSS-compliant tool
5. Integrate generated UVM/C tests into UVM test bench using SV interfaces and DPI-C (details will be provided)
6. Compile and simulate the TB (running tests on target platforms)

This methodology facilitates HW/SW co-verification, helping verification engineers and teams improve SoC verification by writing one PSS model that can execute C-Tests as well as UVM sequences to cover the different aspects of HW/SW co-verification.

These methodologies facilitate a more thorough and efficient verification process by enabling higher levels of automation and abstraction. The integration of PSS, UVM, and C++ in HW/SW co-verification not only streamlines the verification process but also enhances the quality and reliability of SoC designs.

For a fuller treatment on how this PSS-based framework will improve your hardware and software co-verification techniques, please read the new paper from Siemens EDA, A novel approach for HW/SW co-verification: Leveraging PSS to orchestrate UVM and C tests. The paper also shares two use models that walk you through the proposed methodology in detail.

Wael Mahmoud is a quality assurance manager at Siemens EDA, managing various simulation products within the Questa family of products. He holds a B.S. degree in Computer Engineering from Ain Shams University, Cairo, Egypt.

Tom Fitzpatrick is a strategic verification architect at Siemens Digital Industries Software (Siemens EDA) where he works on developing advanced verification methodologies, languages, and standards. Fitzpatrick holds a master’s and bachelor’s degrees in electrical engineering and computer science from MIT.

Vishal Baskar is a product engineer for QuestaSIM and Visualizer Debug Environment at Siemens EDA. He graduated from Portland State University and holds a master’s degree in electrical and computer engineering.

Mohamed Nafea is a technical QA lead engineer for the Siemens PSS-compliant tool. He joined Mentor Graphics (now Siemens) in 2016 to work on the Questa inFact product, specializing as well in constraint random testing, coverage driven verification, and UVM. Nafea holds a Bachelor of Engineering degree in Electronics and a Master of Science degree from Cairo University Faculty of Engineering with a focus on high-level synthesis for AI accelerator development.