tag: PSS

Rebalancing Test And Yield In IC Manufacturing
By Gregory Haley - 07 Nov, 2023 - Comments: 0

Balancing yield and test is essential to semiconductor manufacturing, but it's becoming harder to determine how much weight to give one versus the other as chips become more specialized for different applications. Yield focuses on maximizing the number of functional chips from a production batch, while test aims to ensure that each chip meets rigorous quality and performance standards. And w... » read more

What Happened To Portable Stimulus?
By Brian Bailey - 28 Sep, 2023 - Comments: 0

In June 2018, Accellera released the initial version of the Portable Test and Stimulus Standard (PSS), a new verification language that was slated to be the first new abstraction defined within EDA for a couple of decades. So what happened to it? Apart from a few updates at DVCon, there appears to be little talk about it today. However, the industry has its head down trying to make it work, ... » read more

Chips Getting More Secure, But Not Quickly Enough
By Ed Sperling - 22 May, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the impact of heterogeneous integration, more advanced RISC-V designs, and a growing awareness of security threats, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketin... » read more

What’s Required To Secure Chips
By Ed Sperling - 06 Apr, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about how to verify that a semiconductor design will be secure, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketing at Expedera; and Dave Kelf, CEO of Breker Verification. ... » read more

Software-Driven and System-Level Tests Drive Chip Quality
By Bryon Moyer - 08 Mar, 2022 - Comments: 0

Traditional semiconductor testing typically involves tests executed by automatic test equipment (ATE). But engineers are beginning to favor an additional late-test pass that tests systems-on-chip (SoCs) in a system context in order to catch design issues prior to end-product assembly. “System-level test (SLT) gives a high-volume environment where you can test the hardware and software toge... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Apr, 2021 - Comments: 0

Siemens Digital Industries Software will acquire OneSpin Solutions, a provider of formal verification tools. The company's portfolio of formal tools and apps covers a wide range of design verification, equivalence checking, and functional safety, as well as solutions for trust and security checking. Siemens plants to add OneSpin's technology to the Xcelerator portfolio of verification tools. ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 20 Nov, 2020 - Comments: 0

Synopsys acquired Light Tec, a provider of optical scattering measurements and measurement equipment. The company also provides optical engineering consulting services plus training for use of Synopsys' lighting simulation software. "Light Tec's proven optical measurement capabilities provide our customers with robust new tools for high-accuracy optical product simulations and visualizations," ... » read more

The Next Big Leap: Energy Optimization
By Brian Bailey - 16 Nov, 2020 - Comments: 1

The relationship between power and energy is technically simple, but its implication on the EDA flow is enormous. There are no tools or flows today that allow you to analyze, implement, and optimize a design for energy consumption, and getting to that point will require a paradigm shift within the semiconductor industry. The industry talks a lot about power, and power may have become a more ... » read more

Confusion Persists In Verification Terms
By Brian Bailey - 27 Aug, 2020 - Comments: 7

I find it amazing that an area of technology that attempts to show, beyond a reasonable doubt, that a design will work before it is constructed can be so bad at getting some basic things right. I am talking about verification terminology. I have been in this industry for over 40 years and it is not improving. In fact, it is getting worse. The number of calls I have with people where they hav... » read more

Why Is PSS So Important?
By Ed Sperling - 25 Feb, 2020 - Comments: 0

Robert Hoogenstryd, product marketing manager at Mentor, a Siemens Business, talks about the new testbench verification language standard, what are the big advantages of using PSS, what kinds of challenges this language solves, and how much time this approach can save. » read more

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