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SLM Is Changing The Complete Device Lifecycle Process

Enabling heightened levels of visibility in device performance, reliability, and security with silicon lifecycle management.

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Amit Sanghani, Vice President of Engineering, HW-Analytics and Test Group at Synopsys, discusses how Silicon Lifecycle Management (SLM) is changing the way we look at the complete device lifecycle process and how it can enable heightened levels of visibility in device performance, reliability and security. Learn how SLM is well placed to address the challenges that occur at every stage of cutting-edge advanced node design.

Q: What is SLM and how will it change the industry?

Amit Sanghani: Silicon Lifecycle Management (SLM) is all about ensuring that the chip’s successful operation continues through what is potentially a very long lifecycle. The status quo has always been to test parts only once before they are shipped. Past that point their operational integrity and reliability has up until now been relatively unrecorded. As a designer, you get to know the innermost workings of every one of your devices. Yet, once they go into production, you effectively lose all contact and move onto your next project without a moment’s thought to how the previous device might be getting on out in the field. Things are changing in the semiconductor industry and with the emergence of advanced nodes (28nm to 3nm) there needs to be a different approach, especially when it comes to safety-critical applications. This is where SLM has the potential to change the semiconductor industry and the way we think about the cradle to grave journey or our devices.

Q: Why is there a requirement for SLM?

Sanghani: The SLM platform was born out of a desire from customers to test devices once they had powered on the device. This requirement has since evolved with additional requests to test periodically, look at security and monitor for parameters like performance. The SLM platform has been built on a strong foundation based on Synopsys’ experience and strength within the TEST and DFT space and drawing on expertise in embedded monitoring and sensing, data analytics and yield management. This data can then also be used to reanalyze and improve earlier stages of the lifecycle.

Q: What makes the Synopsys SLM approach different?

Sanghani: The SLM platform leverages existing industry leading components to address the challenges of quality and reliability associated with today’s electronic systems’ growing complexity. Offering solutions to these challenges is nothing new but the approach we are using is. By providing our customers access to device data throughout the entire chip life span, we enable a process of on-going ‘in life’ feedback and optimization. At the heart of this is a specialized analytics system that will allow a more efficient and effective way to address these challenges. SLM has two underlying principles: firstly, gather as much useful data about each device as possible and secondly analyze the data throughout the entire lifecycle to obtain actionable insights to improve chip and system-related activities.

Q: What are the key hardware and software components of the SLM platform?

Sanghani: At its foundation, there is the hardware, the PVT monitors, environmental sensors and other monitors that provide the rich silicon data that the whole process relies on. Then, the software is integrated into the test equipment for intelligent data extraction and embedded in the target system for local analysis. These hardware and software elements then feed data into the unified SLM Database and data models that cover all semiconductor lifecycle stages with analytics engines targeted to each of the stages, including design calibration, product ramp, test and manufacturing and in-field maintenance.

Q: I’m working on advanced node SoCs, how does SLM relate to me and my design?

Sanghani: In applications where silicon performance and reliability are critical such as data center, AI, high-performance computing and automotive, quality, security and reliability are growing concerns that cost companies billions of dollars to monitor and address. SLM gives designers the ability to keep track of and maintain silicon data across multiple devices in multiple systems, and this allows them to identify systematic issues that may occur over a large population of devices and systems. SLM

Q: How would I implement it?

Sanghani: The SLM process begins by implementing some key silicon building blocks in the form of embedded in-chip PVT monitors and structural sensors that essentially act as the eyes, ears and other senses of the device, providing deep visibility levels. This extracted silicon data is then used to calibrate design modeling parameters. Data from ring oscillator measurements, critical path test results and process/voltage/temperature (PVT) monitors are examples of this data. These data collection tools then feed the system with the raw data coupled with intelligent integration automation. Targeted analytics is then performed at each lifecycle stage to drive optimizations specific to each phase.

Q: What are the benefits of Silicon Lifecycle Management?

Sanghani: SLM provides numerous benefits to not only the chip designer but also the end user of the chip. These include smoother and faster product bring-up, enhanced performance and security over the life of the chip. Other benefits include improved design performance, faster product yield ramp, higher quality yield, test time reduction and improved product quality. This in turn, means a faster time to market for the chips and systems themselves.

In summary, SLM is applicable to many different areas from early design, manufacturing, test, debug and bring up, right through the in-field operation. Synopsys’ SLM platform closes the silicon loop through the analysis of on-chip monitor and sensor data to optimize all phases of the silicon lifecycle in what signifies a new way forward in chip design and ongoing maintenance. Imagine a future where you can continue this relationship with the device and track and monitor it progress for its entire lifespan, this has the potential to be a game- changer for the advanced node semiconductor design community.



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