Smart Early ASIC Design Prototyping And Analysis

The Power Delivery Network (PDN) is the backbone of ASIC design. It is used to supply clean power to active circuits in the IC. Voltage drop on the power rails can result in degraded performance, making delivery of noise free supply to all design elements including die, package and PCB, a challenging task.

With increasing competition in the market, delivering chips on time with ‘first silicon success’ has become more important than ever. Mobile SoC design companies are releasing two to three chips per year, reducing their design cycle to six months or less. We see emerging mobile handset manufacturers challenging established SoC companies on cost and performance of their devices. To cut fabrication costs, every square millimeter of metal and die area becomes precious. If design prototyping is not done or incorrectly performed, failure in later stages of the design can prove to be very costly.

Fig. 1: Cost of failure w.r.t Design Cycle Phase

Designers are trying to squeeze maximum logic into minimum chip area with hard-to-achieve processing power. To meet this demand, the industry is moving toward finFETs to achieve maximum performance with minimum power. But at lower technologies, power grid design is becoming even more challenging due to high power density, lower supply voltages and higher operating frequencies. IR, electro-migration (EM) and ESD are already nightmares for designers. On top of this, designs deploy complex methods such as MTCMOS power gating, DVFS and LDO making it more challenging.

For years, power sign-off began with either pen and paper calculations, or SPICE experiments applied on small representative designs. Nothing much has changed in the last decade, and although various techniques are available, the usage of these algorithms in large designs has not been practical. Power grid specs use traditional approaches, and these same specs are re-used in multiple designs even though the scope of design itself has changed. The drawback of the typical power grid prototyping flow illustrated below is that some of the high power blocks can result in serious performance issues, while some of the low power blocks end up with over-designed power/ground (PG) grid.

Fig 2. Typical Power Grid Prototyping Flow

Fig 3:  Power Density Aware PG prototyping

There is a need for smart PG grid prototyping, with high-performance blocks getting a more robust grid as compared to low-power blocks. Many companies follow the pessimistic approach of inserting the highest possible amount of metal layers with many layers dedicated for power routing, but this approach is not feasible in the current competitive market. By dedicating so many metal layers for power, a designer will face signal routing congestions issues, especially with so many devices on a chip. It is time to adopt better approaches for early PDN design that leverage complex theories and specific EDA tools.

PG grid optimization is just one aspect of PDN prototyping. We also need proper planning for ESD clamps, power switches, LDO insertion, decap insertion, etc. as shown in the diagram below.

Fig. 4: Essentials of PDN Design

Failures happening late in the design cycle are more costly and can have a significant impact on tape-out schedules. Some examples of bad power planning are shown below.

Fig. 5: Typical On-Die Power Planning Issues

When performing power grid optimization, one needs to understand the factors affecting the grid optimization. For example, sensitivity of the die grid needs to be understood. For Static IR drop, the sensitivity of grid depends on the following main factors:

1. Power density and activity in an area;
2. Number of available power/ground sources;
3. Number of domains in a chip and the metal density occupation per domain, and
4. Number of power gates in the area.

Fig. 6: Grid Prototyping

If you are looking at dynamic IR drop, then there are number of additional factors such as simultaneous switching, decap addition, etc. Careful power planning at an early stage needs complete understanding of all the sensitivity factors.

To perform early static or DC analysis the following information is needed:

• Chip boundary or floor plan DEF;
• Sample bump placement;
• Sample switch placement (if power gated design);
• Power or current assignment on metals/vias in the absence of standard cell placement or block data.

Additionally, early dynamic or transient analysis needs the following information:

• Dynamic current profiles like PWL waveforms.
• Dynamic capacitance values for decap estimation like nF/sq mm

Inclusion of prototyped package RLCs help eliminate many of the basic issues such as bump placement, switch insertion, decap efficiency, etc., during early IR (static and dynamic) analysis.

Early dynamic analysis for power gated designs should include rush current analysis. This helps designers determine various topologies of switch insertion and power-up sequence such as daisy chains.

Fig. 7: Switch Delay vs. Peak Rush Current

Early analysis not only applies to the die, but also to package and PCB. Providing the package designer some representative values of on-die capacitance can help tune package parasitics such as package decap to avoid resonance.

Some EDA tools can provide SPICE macromodels, which can be used by package designers for highly accurate AC/DC/transient analyses. In addition, designers also can create advanced models for doing system-level thermal or EMI analysis.

Fig. 8: Die-Package AC Co-Analysis Eliminates Resonance Issues

The need for ensuring power and signal integrity on a system-level basis is required, and with tight delivery timelines, ‘going early’ should be an essential approach to design analysis.