Why Chips Die


Semiconductor devices contain hundreds of millions of transistors operating at extreme temperatures and in hostile environments, so it should come as no surprise that many of these devices fail to operate as expected or have a finite lifetime. Some devices never make it out of the lab and many others die in the fab. It is hoped that most devices released into products will survive until they be... » read more

Designers Face Growing Problems With On-Chip Power Distribution


The technology evolution in semiconductor manufacturing has led to chips with ever-higher power densities, which is leading to serious problems with on-chip power distribution. Specifically, the problems surrounding voltage drop—or IR drop (from V=IxR)—have become so acute that we have seen multiple companies starting to get back dead silicon from the fab. For example, a recent 7nm chip ... » read more

Tech Talk: 7nm Process Variation


Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond. https://youtu.be/WHNjFr1Da6s » read more

The Implementation Of Embedded PVT Monitoring Subsystems In Today’s Cutting Edge Technologies


This new whitepaper from Moortec takes a comprehensive look at the Implementation of Embedded PVT Monitoring Subsystems in Today’s Cutting Edge Technologies and how this can benefit today’s advanced node semiconductor design engineers by improving the performance and reliability of SoC designs. With advances in CMOS technology, and the scaling of transistor channel lengths to nanometer (nm)... » read more

Managing Voltage Drop At 10/7nm


Power integrity is becoming a bigger problem at 10/7nm because existing tools such as static analysis no longer are sufficient. Power integrity is a function of static and dynamic voltage drop in the power delivery network. And until recently, static analysis did an effective job in measuring the overall robustness of PDN connectivity. As such, it is a proxy for PDN strength. The problem is ... » read more

Closing The Power Integrity Gap


Voltage drop has always been a significant challenge. As far back as 130nm, specialist tools were being used to ensure that enough local decoupling capacitance (decap) cells were inserted in addition to larger decaps implemented around the SoC. But advanced nodes are complicating matters and further increasing complexity. These technological challenges, which underlie the power, performance ... » read more

Accurate Thermal Analysis, Including Thermal Coupling Of On-Chip Hot Interconnect


Driven by rapid advancement in mobile/server computing and automotive/communications, SoCs are experiencing a fast pace of functional integration along with technology scaling. Advanced low power techniques are widely used, while meeting higher performance requirements using a variety of packaging technologies. The Internet of Things (IoT) is further opening up new applications with connected d... » read more

Two Constraints-Based Techniques To Address Power-Related Challenges In SoC Design


Power scheduling, power integrity targets, voltage drop—these are just a few of the power-related challenges you’re no doubt managing in your SoC designs. There aren’t any easy answers, but there are some emerging—and promising—techniques. Two such techniques, according to University of Toronto Professor Farid Najm, are constraints generation and constraints-based verification. “... » read more

How To Fix Common Power Problems


As the industry moves to ever more advanced technology nodes, managing power has emerged as a primary challenge in modern SoC design. With smaller nodes, the wires become taller and narrower, which increases the resistivity and leads to more pronounced voltage drop effects. Electro-migration effects are also more severe at advanced nodes, causing serious reliability concerns. Both RTL synthesis... » read more

Smart Early ASIC Design Prototyping And Analysis


The Power Delivery Network (PDN) is the backbone of ASIC design. It is used to supply clean power to active circuits in the IC. Voltage drop on the power rails can result in degraded performance, making delivery of noise free supply to all design elements including die, package and PCB, a challenging task. With increasing competition in the market, delivering chips on time with 'first silico... » read more

← Older posts