Is Common Resistance Affecting Your Analog Design Reliability And Performance?

The increasing size of full-chip layouts and higher complexity requires a more application-specific and smarter extraction analysis.


Integrated circuit (IC) design reliability has always been important and essential to market success. After all, if no one could count on your product to operate as designed, and for as long as intended, there wouldn’t be many buyers!

However, given the increase in the types and complexity of design applications, coupled with the increasing technological challenge of manufacturing at advanced nodes, ensuring that reliability has become a much more challenging process. Reliability design rules and their corresponding checks that focus on complex reliability conditions and potential issues have become a critical function in IC design verification and tapeout.

While full-chip parasitic extraction with post-layout simulation has long been one of the fundamental phases of IC design verification, the increasing size of full-chip layouts and the higher complexity of both designs and process technologies require a more application-specific and smarter extraction analysis specifically designed for interconnect parameters.

For example, one such parameter is interconnect common resistance. Reliability in IC design relates to both physical and operational reliability, either of which can be impacted by the effect of interconnect resistance [1-4]. However, an accurate analysis of this impact for analog designs requires an understanding of common resistance and how it affects IC performance. Extraction of the interconnect common resistance of a net is an important component in multiple reliability verification flows, such as noise analysis [5] and electrostatic discharge (ESD) point-to-point (P2P) resistance verification [6].

Net common resistance

All nets connect multiple devices. The common resistance of a net is determined by the common segments of that net from a given starting point, before the net branches to the connected devices. Figure 1 shows the common resistance segment for a target net in both a topology schematic and a physical layout.

Figure 1: Schematic showing common segment topology for a net connecting a pad with multiple blocks [5], and the common resistance segment highlighted in a physical layout.

Noise & voltage drop analysis

In analog design layouts, interconnect branching is commonly used to connect multiple devices or blocks on a net. The common resistance value of a net is critical information when performing both noise and overall voltage drop analysis.

Noise, which is a spontaneous fluctuation in current or voltage, can be propagated between different blocks through common nets, such as power nets. Noise is generally undesirable, because it causes fluctuations in the intended signal level. Because of this impact, noise analysis is a fundamental aspect of circuit reliability verification.

When the common resistance between two blocks is high, noise avoids this resistance and propagates from the source block to neighbor blocks, increasing the effect of noise on the neighbor blocks. When the common resistance is low, the noise propagates to the top ports instead, minimizing the noise effect on other blocks. Figure 2 shows the impact of common resistance on noise analysis [5].

Figure 2: Noise propagation between blocks is affected by the amount of common resistance (Rcommon) of the connecting net [5].

To avoid noise propagation between blocks, designers must verify that the common resistance is below a specific threshold. This constraint can be easily validated on a layout prior to a full extraction and noise simulation of the full design.

Voltage drop
Voltage drop analysis is another essential process in analog layout design. Current flows through the interconnect to feed transistors, but interconnect resistance can create a drop in voltage equal to the current multiplied by the resistance. The voltage drop across the interconnect due to parasitic resistance of the common segments on these nets is seen by all the connecting devices. Voltage drop analysis must include the common resistance value to enable designers to determine the actual voltages that arrive at the transistors.

ESD analysis

Ensuring adequate protection against ESD events is a critical reliability check that is required by many foundries [7].

ESD protection circuits can be created using a rail clamp strategy, which uses diodes connected to the I/O pad and the local VDD and VSS of the I/O block [6]. These diodes are intended to operate only in forward-biased mode, shunting any positive ESD discharge to VDD and any negative ESD discharge to VSS. A positive discharge to VSS or a negative discharge to VDD as reference ground requires a further discharge path between VDD and the VSS bus, which is provided by the power rail clamp. In most critical discharge paths, there is a series path composed of a diode, a portion of the supply bus with relative resistance, and the rail clamp device.

To avoid damaging the protected devices, the voltage across this entire protection path must not exceed a critical limit [6], defined as:

VESD_Clamp_Path < VFailure_Circuit

ESD protection circuits exhibit resistance behavior similar to any analog circuit layout. Typical measurement starts from the IO pad and moves to power or ground through the ESD protection devices. Because this type of measurement can’t determine the branching point of the current, there is no way to exclude the common resistance value.

However, when an ESD event occurs, the voltage drop created by common resistance is not experienced by the protected devices. Consequently, common resistance must be excluded when evaluating the P2P resistance measurement against the maximum threshold, because it has no effect on ESD events. If designers fail to remove common resistance from their measurement, results will erode actual design margins, due to the reporting of larger than expected ESD resistances.

Figure 3 shows an ESD protection scheme in which the P2P resistance measurement from the IO pad to the primary ESD pull-up and pull-down primary protection devices must be below a specified threshold to adequately protect the circuit from ESD events.

Figure 3: ESD protection structure showing common resistance of an IO pad net.

P2P resistance ESD checks must accurately exclude the common resistance to validate that the resistance between top pads to ESD protection devices is below the maximum threshold.

Common resistance checking

To help design teams adequately assess reliability conditions in their designs, electronic design automation (EDA) tools like the Calibre PERC reliability platform support P2P resistance and current density interconnect resistance extraction [8]. To simplify the process, the Calibre PERC reliability platform also includes a packaged checks framework that provides a variety of pre-coded checks. Designers can configure and run these checks directly on their design, without the need for custom rule check coding at runtime [9].

A common resistance check, which extracts the common resistance of given interconnect, is one of the checks included in this framework. The results of this check are displayed in the Calibre RVE results viewing interface, and can also be used with the Calibre DESIGNrev layout viewing interface to visually display and highlight the common segments on the layout. Once calculated, this value can be automatically applied where required, in checks such as ESD resistance calculation. Figure 4 shows the results of a Calibre PERC common resistance check for a target net.

Figure 4: Results of a Calibre PERC common resistance check are highlighted using the Calibre DESIGNrev and Calibre RVE interfaces.


Circuit reliability is a critical success factor in analog design. In particular, common resistance calculation is a crucial element when performing noise and voltage drop analysis, as well as verifying ESD protection. Understanding the correct treatment of common resistance in analog circuit and reliability verification is essential to achieving the designed performance and reliability targets. As designs get larger and more complex, taking advantage of automated packaged common resistance checks ensures accurate, fast, and efficient resistance measurements, while also enabling fast and accurate debugging of any errors detected.


  1. S. Oates, “Interconnect reliability challenges for technology scaling: A circuit focus,” 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), San Jose, CA, 2016, pp. 59-59.
  2. J. Clement, “Electromigration modeling for integrated circuit interconnect reliability analysis,” IEEE Transactions on Device and Materials Reliability, vol. 1, no. 1, pp. 33-42, March 2001.
  3. Tsong-Ming Chen and M. Yassine, “Electrical noise and VLSI interconnect reliability,” IEEE Transactions on Electron Devices, vol. 41, no. 11, pp. 2165-2172, Nov. 1994.
  4. Derong Yan, “Ensuring Robust ESD Protection in IC Designs,” Mentor, a Siemens Oct. 2017.
  5. Shuichi Teramoto and Kunihiro Yanagida, “Comprehensive Power Rail Constraint Verification for Large Analog Designs at Early Stage,” DAC
  6. ESD Association, “ESD 0-01-11,” Technical Report for ESD Electronic Design Automation Checks, 2011.
  7. Matthew Hogan, “Jumpstart your reliability verification with foundry-supported rule decks”, Mentor, a Siemens Business. July 2018.
  8. Mentor, a Siemens Business, “Calibre PERC reliability verification ”
  9. Hossam Sarhan, “Configurable, easy-to-use, packaged reliability checks,” Mentor, a Siemens May 2019.

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