Smarter Clock Gating

What’s needed is more efficient clock gating, not more clock gating.

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By Ghulam Nurie
With the proliferation of mobile devices, power consumption and battery life have emerged as significant concerns during chip design. There are many different techniques used for power optimization, but of all the different techniques, clock gating is the most popular and widely used technique, according to a blind, anonymous survey emailed to several thousand participants worldwide in December 2011.

Unfortunately, a common misconception among designers is that the higher the percentage of registers gated, the higher the power savings. Thus, many designers aim to get as many registers gated as possible. But more important than the number of registers gated, is the efficiency of the gated register over time.

Here’s why: Simply counting the number of registers with clock gates is not a good measure of power savings because it does not take into account how long the register is gated (turned off) under typical use mode. In the figure below, a hypothetical one-register design is 100% clock-gated. However, if you look at the switching activity on the enable (EN) signal you will see the enable is low 3 out of 10 clock cycles. Consequently, the clock-gating efficiency is 30%.

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Clock-gating efficiency is a much better indicator of the dynamic power savings achieved by clock gating because it takes into account the switching activity in the design. Efficiently gated flops use less power since power tracks with the total number of actively clocked flops in a design.

In his paper titled “Implementing an Efficient RTL Clock Gating Analysis Flow at AMD,” Steve Kommrusch describes a methodology where AMD used clock-gating efficiency to select the optimum clock gating scheme, which reduced dynamic power by 20% on an SoC that was already finely tuned for power. AMD identified efficient clock gating opportunities and selected the most efficient ones to gate. In AMD’s experience, the percentage power savings identified by PowerPro at the RTL directly correlated with PTPX power estimates at the gate level. www.calypto.com

In summary, it is not the percentage of registers gated that matters—it is the gating efficiency that results in improved power savings. Only by fully understanding gating efficiency can the user make intelligent and efficient decisions the best way to yield maximum power savings from this approach.

—Ghulam Nurie is director of marketing at Calypto Design Systems.