What’s needed is an automated, reliable and flexible solution with hooks to capture and modify the existing design and add new functionality.
Today’s system-on-a-chip (SoC) designs are creating more challenges than ever – challenges that demand bringing the product to market faster, before the competition does. The electronics industry and growing competition require that SoC’s achieve a short time to market (TTM) while design complexity continues to grow at a rapid rate. Another challenge is to keep the SoC design and overall product costs as low as possible.
How can design companies meet such challenges as TTM, design complexity and competitive differentiation while keeping costs down? With ever-shortening TTM, one way is through IP reuse. This implies building a solid, extensible architectural platform and deriving newer platforms from it as per the application needs, which reduces design time and increases success rate. There is a need to address the difficulties that design companies are facing today to create derivative designs. As we are in the era of highly complex giga-scale products, the error margin or the tolerance guard band is getting tighter and tighter with respect to previous design approaches.
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