SoC Integration Mistakes

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion.

SE: Are the integration problems different from a couple nodes ago, or are there just more of them?

Capodieci: There are cultural problems. Big design houses or advanced IP developers have already incorporated into their culture yield analysis and manufacturability, but it is not homogeneous across the landscape. We have implemented scoring for manufacturability and yield, but we have very inhomogeneous input. Our first goal is to normalize everything. But that’s just the beginning. We have situation where the equivalent of margin in the manufacturing world is using the recommended design rules wisely and taking advantage of all the white space. People still interpret the design manual in many different ways. If they say this is a minimum rule, everyone sticks with the minimum rule even if there is a chance to use more space or make the lines wider. We can really tell different design teams apart from how much they’ve learned. Right now we have situations where some of our customers are asking us to partner directly with some of their IP partners to do advanced programs for IP certification and validation. Are we seeing more problems? Yes, and there are differences in the quality of how well people handle those problems.

SE: What happens with IP when we move to 10nm, where we have higher-mobility materials and less flexibility in terms of margin, power, more physical effects and bigger chips.

Castagnetti: 10nm is 2016. IP teams should have started on this already. That’s the challenge. How do you get things done ahead of time to get to a certain level of maturity? That’s what we see more of today. It’s co-development, and that has challenges. You can request more verification from the IP supplier, but when it’s time to tape out you have to go with what you have.

Aitken: There are two interesting angles for IP and 10nm. For the higher-level IP, such as the processors, the design of the microarchitecture really needs to be tuned to the process. So the L1 cache is one of the tightest timing paths, so the relative speed of logic and memory at the node is really going to matter. Then at the low level, the question is whether you’re going to triple pattern these zeroes or double pattern them, because that makes a big difference in our library. What we want to do with the foundries is have a discussion. ‘If this rule is this many nanometers and we want it to be one less nanometer, is that a cliff for you or not? If we give up the nanometer here, can we get another one over there? If we double pattern this, can we single pattern that?’ That kind of discussion makes for a much more usable form of standard cell IP than you can get otherwise. We tried to work with the foundries earlier and the response we got back was, ‘We don’t know. That process hasn’t been invented yet.’ So we came up with a concept of predictive technology. We take our best guesses of what the technology is going to be.

SE: Is that based on what you know so far?

Aitken: Yes. And we may be wrong, but at least we’re in the ballpark. Then we take our ideas of what these are going to be and we develop standard cells.

Capodieci: This is correct because the 10nm node is going to be very emblematic of what I call Schrodinger’s IP, where you’re going to have a multiplicity of options. Everything may require three or four different alternatives because the underlying process technology—which also means the fundamental ground rules—has not been fixed yet. I would challenge any foundry, and even Intel, to offer certainties at this time. There is a virtual or Schrodinger effect, where you can have multiple possibilities. Eventually, we’ll approach one. Or maybe there will be more than one. Will this be done by double patterning or triple patterning or quadruple patterning. If EUV will be available, which is still in doubt, then different IP will have different ground rules. There is a range. Or you can design everything in a very regular way so you are ready for whatever type of process there will be.

SE: So how does this work if you don’t know what exactly you’re going to be designing to?

Lefferts: Even at 14nm or 16nm, we’ve been developing IP using a very early version of the PDK and going through changes throughout the development process. That’s not going to change at 10nm. It’s going to be a moving target. That won’t get better.

SE: And that goes back to margin, programmability and many other pieces, right?

Lefferts: I’ve definitely seen a transition from designs that we did back in 2000 versus now. In 2000, you’d do a design, take your time, get it right the first time, with no plans to touch it again. That’s a horrible idea if you’re doing it with a 0.1 version of a PDK. You know the PDK is going to change. The perfect job you’ve done is going to change when you get a new deck. So what ends up happening is everything overlaps. You used to have an object. Now you have a Gaussian (distribution). It happens through the entire IP development cycle. The analog guys have to put enough stuff together to freeze the design and give it to the visual team, so they have something to work on. They can’t wait until you’re done. They have to start when you start. So everything is done in overlays. You do the analog design, you lock the pins, you give it to the digital guys, they start doing place and route, and this continues over and over and over.

SE: But even the 1.0 version of a PDK isn’t the end, right?

Lefferts: No, 1.0 is just the first one. My team is responsible for downloading all of the foundry data at Synopsys. We have one team downloading the same data for everyone in the company, so anyone working on IP gets it from the same place. If you look at how many drops of each technology we have and couple that with the number of technologies, it’s a very large number. There are already more than a dozen drops on 16nm. That will continue on 10nm. They’re making it up as they go. This is a similar discussion to what we did at the chip level. We did the floor plan knowing it would change. We lined up our assumptions, and we did it again and again.

Murphy: As you go down in process technology, things are becoming more and more strongly coupled again. You’re starting to lose this decoupling between the IP supplier and the integrator because you have to have more and more support and more and more help to put these IPs together. There is a possibility that we may have to focus on decoupling, where feasible. But how do you do that? Do you help with timing? Do you put a wrapper around the IP? Can you make these IPs more islands unto themselves.

SE: Isn’t that what’s being discussed with subsystems and 2.5D and 3D stacked die?

Lefferts: We see where IP designers want to do one block and walk away from it. They have to change the methodology to come back and fine tune. It’s a different way of working. You have to be able to iterate through that process to the last release of everything. You could try to partition it differently. We’re already making break points throughout this process. There’s a drop point for the digital, and then it goes to the next level up, and then the customer gets a drop. There might be a creative way to absorb change in a layer, but it also runs the risk of adding a whole bunch of margin you didn’t need. Maybe you’re making your Dcaps too big because you’re being too conservative.

Murphy: So does the IP business trend back to being a service business rather than a product business?

Aitken: It’ can’t. The physical IP has to influence what the foundry is doing, and the physical constraints of the foundry have to influence the IP. That doesn’t mean it isn’t an IP business. It’s a very challenging job that doesn’t make sense to doing once or a couple times rather than having every chip team try to do that on their own. The same is true at the high level, as well. Developing a microprocessor is an enormously complicated thing. You let one company do it well.

Castagnetti: It’s not economical. We’ve seen people try to do IP that was custom for every customer. What breaks is what you can gain from third-party IP, which is the shared wealth of experience in terms of where this IP was used and how many people have used it. As soon as you customize it, that becomes challenging for the IP provider to support and it becomes a challenge at the end for the integrators. I like the idea of keeping IP as generic as possible and adding your secret layer on top as an integrator in a way you can not mess with the IP. To do that, it becomes important to have a sufficient amount of information. For instance, how well-defined is the interface between what the IP guys do and what I do? That’s one of the key pieces.

To view part one of this roundtable discussion, click here.
To view part two of this roundtable discussion, click here.