SoC Physical Closure Begins At RTL

Why completeness of verification and physical design closure for area, timing and power can impact quality and schedule for SoC development.

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Any survey of chip design teams consistently points to two problem areas impacting quality and schedule of today’s SoCs. Those areas are: a) completeness of verification, and b) physical design closure for area, timing and power for complex IP’s and SoC’s. With the advent of deep sub-micron technology, these problem areas have become exacerbated. In this White Paper, we take a closer look at the physical design closure aspects of advanced SoCs. We provide a root cause analysis of unpredictable physical design closure issues and explore possible solutions and methodologies to address these problems.

To download this paper, click here.


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