Something Old, Something New

As older process technologies become more useful, it’s time to clean them up.

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Sooner or later, everything comes back into vogue. There are only so many permutations of fashion, architecture and other designs, and eventually something has to be recycled, even if it’s an antique.

Technology is no different than fashion. In the late 1990s, when governments and banks were preparing for the Y2K problem, people with knowledge of assembly code were in extremely high demand because most of their peers had long since retired. It wasn’t unusual to see job openings paying several hundreds of thousands of dollars—multiples of their original salaries—for software developers who could rewrite assembly code.

The semiconductor industry has been relatively insulated from this phenomenon. Moore’s Law has guaranteed that the industry moves forward every couple years with no need to look back. Progress has been defined by the next node, no matter where you are on the road map. DRC decks and libraries have been updated at each new node, and design rules and exceptions have been meticulously worked out as processes mature.

Two things are forcing changes to that way of thinking. First, it’s no longer economically advantageous to move to the latest process node. Those at the leading edge nodes are not finding that cost per transistor is going down in the finFET and double-patterning, multi-patterning era. There are still advantages in terms of leakage current, performance and density, but the actual cost of designs from inception to chip isn’t so easy to calculate. Chipmakers, EDA companies and foundries are simultaneously developing the processes, the design rules, and the exceptions to those rules, raising the stakes for everyone involved.

Second, established nodes are getting a makeover as companies opt to squeeze more out of those nodes instead of shrinking features. At 40nm, physical effects are far less than at 16nm. At 28nm, fully-depleted silicon on insulator (FD-SOI) and biasing avoid the need for finFETs and the resulting dynamic power density increase at 14/16nm, as well as the need for double patterning. That’s becoming particularly attractive for IoT devices, which are likely to be manufactured with updated processes at 28nm, 40/45/55nm, and 90nm.

And therein lies the problem. As Mentor’s Michael White observed, “The folks who defined the DRC deck for 90nm and 65nm have retired.” Streamlining the process and adding design freedom by getting rid of rules that no longer are needed would be a monumental effort. It would be much simpler if the people who created those rules could say why they were needed in the first place.

There are workarounds. Pattern matching is one alternative. But getting rid of unnecessary rules is like getting rid of unnecessary standards. They’re burdensome, limiting, and they never seem to completely go away because it’s too expensive to go back and re-do all the work that was done in creating those rules. But that doesn’t mean effort shouldn’t be made to re-examine the old rules and better document why they were implemented in the first place.

This is a new problem for the semiconductor industry, which isn’t in the habit of investing in older things. It’s also a problem that will continue to plague designers as more designs are created at established nodes and more tweaks are made to the older processes. Older nodes are now back in vogue, and it’s time to polish them up.