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SpZip: Architectural Support for Effective Data Compression In Irregular Applications

SpZip, an architectural approach that makes data compression practical for irregular algorithms

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Published in: 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)
Yifan Yang (MIT); Joel Emer (MIT / NVIDIA); Daniel Sanchez (MIT)

Abstract:
“Irregular applications, such as graph analytics and sparse linear algebra, exhibit frequent indirect, data-dependent accesses to single or short sequences of elements that cause high main memory traffic and limit performance. Data compression is a promising way to accelerate irregular applications by reducing memory traffic. However, software compression adds substantial overheads, and prior hardware compression techniques work poorly on the complex access patterns of irregular applications.We present SpZip, an architectural approach that makes data compression practical for irregular algorithms. SpZip accelerates the traversal, decompression, and compression of the data structures used by irregular applications. In addition, these activities run in a decoupled fashion, hiding both memory access and decompression latencies. To support the wide range of access patterns in these applications, SpZip is programmable, and uses a novel Dataflow Configuration Language to specify programs that traverse and generate compressed data. Our SpZip implementation leverages dataflow execution and time-multiplexing to implement programmability cheaply. We evaluate SpZip on a simulated multicore system running a broad set of graph and linear algebra algorithms. SpZip outperforms prior state-of-the art software-only (hardware-accelerated) systems by gmean 3.0× (1.5×) and reduces memory traffic by 1.7× (1.4×). These benefits stem from both reducing data movement due to compression, and offloading expensive traversal and (de)compression operations.”

Y. Yang, J. S. Emer and D. Sanchez, “SpZip: Architectural Support for Effective Data Compression In Irregular Applications,” 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, pp. 1069-1082, doi: 10.1109/ISCA52012.2021.00087.



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