A No-Compromise Approach To DFT
The increasing complexity in large System on Chip (SoC) designs present challenges to design-for-test (DFT). Hierarchical DFT alleviates some of those challenges, by itself, is no longer enough. Adding Tessent Streaming Scan Network (SSN) technology eliminates the difficult and costly trade-offs between test implementation effort and manufacturing test cost by decoupling core-level and chip-level DFT requirements. With SSN, a true bottom-up DFT flow DFT is possible.
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