Structural Verification Finds Mixed-Signal LP Errors

By Luke Lang
In the last blog, I gave some reasons why there is no low power (LP) analog/mixed-signal solution. However, this does not mean there is no effort in this area. Toward the end of 2009 and early 2010, I worked with a customer to establish a LP analog/mixed-signal structural verification flow. This flow was proven to be extremely helpful. It caught several LP bugs that were not found by the customer’s existing verification flow.

First, let me give you some background. The customer is a very well-known and reputable LP mixed-signal design company. They have a very advanced analog/mixed-signal modeling and verification flow. However, that flow was based purely on functional simulation.

The majority of the LP design problems can be found by both LP functional and structural verification. Most engineers are familiar with functional simulation, but what is LP structural verification? It is a way to detect LP issues by examining the netlist structure. For example, you might have a domain crossing from a gate that may be switched off to a gate that may be on. This crossing must be protected by an isolation gate. If the isolation gate does not exist, then we know there is an error without needing to run simulation.

Of course, this problem can also be detected by LP functional simulation. However, you must prepare the correct testbench, run a long simulation, and then trace through lots of waveforms to find the problem. Without a question, structural verification is far more efficient.

Being an advanced LP design company, the customer was already familiar with LP structural verification. They had already planned to create a LP black-box model of the mixed-signal block and verify its interfaces to the rest of the SoC. I proposed to take this approach one step further by creating LP black-box models for all analog circuits within the block and verifying all of the LP connections inside the block.

The customer thought this was a good idea and started working on it. Soon, they found the work to be too manually intensive. There were well over 50 analog circuits that needed LP black-box models written. Furthermore, the power intent that was designed into the circuit schematic had to be manually extracted and coded into a CPF file. All of these had to be run through LP structural verification. Despite the work, we pushed on and were rewarded by finding some LP errors that were not detected by LP functional simulation.

The diagram below illustrates a common problem:

In LP functional simulation, the source block is shut off and outputs an X. This X is propagated through an always-on inverter and driven into the receiving block. However, since the receiving block is also shut off, it is not able to observe the X.

LP structural verification detected an off-to-on domain crossing without isolation and flagged an error. Fortunately, these errors were detected in time and fixed. As a result, this complex mixed-signal SoC came back without any LP problems.

From this exercise, we concluded that LP structural verification is not only possible but absolutely necessary for analog/mixed-signal designs. The CPF power intent can also be used to drive LP functional simulation with analog behavioral models. The combination of LP structural and functional verification gave the designer full confidence that the design was free from LP problems. However, the exercise was so manually intensive that no one wishes to repeat it. Currently, work is in progress to automate the creation of CPF power intent and LP black-box models from the circuit schematic.

I firmly believe that in the near future, analog/mixed-signal designers will be able to utilize the same kind of verification technology that the digital designers have used for several years.

–Luke Lang is a staff solutions engineer at Cadence Design Systems.