Accurately predicting chip power and noise requires a consideration of the entire power delivery network.
In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate faster at lower power and to pack more functionality within the same size of silicon. In these process nodes, however, power, noise and reliability sign-off create significant problems arising out of the physics, size and shape of the devices and interconnects.
To reduce dynamic power, the trend is toward using lower supply voltages. However, when devices (particularly FinFET-based ones) are operated at lower voltages, the noise margin significantly reduces. These devices tend to have higher drive strengths, causing higher localized dynamic switching currents that result in higher voltage drop. Accuracy of the dynamic voltage drop analysis thus becomes increasingly important for avoiding voltage drop-based failures. To accurately predict chip power and noise, consideration for the entire power delivery network (PDN), from the chip to package and board, in a voltage drop simulation becomes necessary.
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