Soitec’s Wafer Roadmap for Fully Depleted Planar and 3D/FinFET

By Various Writers - 24 May, 2012 - Comments: 0

The following is a special guest post by Steve Longoria, Senior VP of Worldwide Business Development at Soitec. It first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization. ~~ Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to th... » read more

Margin Call

By Ed Sperling - 03 Feb, 2012 - Comments: 0

Ever since Moore’s Law passed 65nm, the discussion has focused on power versus performance. Do you run a chip faster and hotter, or do you keep performance about the same from one chip to the next and improve battery life. At 28nm and beyond, there are other factors that begin to weigh into this discussion. One is reliability. Can a chip developed at the forefront of Moore’s Law be as re... » read more

The Growing Need For A Systems Approach

By Ed Sperling - 28 Jul, 2011 - Comments: 0

By Gabe Moretti Electronic computing systems have gone through an evolutionary cycle since the invention of the mainframe, and the process is continuing. Semiconductor technology, mostly based on CMOS fabrication methods, has enabled an increase in design complexity and device functionality that have revolutionized the world. But 20nm processes may be the last that obey Newtonian physics. T... » read more

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tag: 14nm

Soitec’s Wafer Roadmap for Fully Depleted Planar and 3D/FinFET

Margin Call

The Growing Need For A Systems Approach