Inside Lithography And Masks

By Mark LaPedus - 05 Apr, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cove... » read more

Fractilia: Pattern Roughness Metrology

By Mark LaPedus - 21 Feb, 2017 - Comments: 1

A new startup has emerged and unveiled a technology that addresses one of the bigger but less understood problems in advanced lithography--pattern roughness. The startup, called Fractilia, is a software-based metrology tool that analyzes the CD-SEM images of pattern roughness on a wafer. Fractilia, a self-funded startup, is led by Chris Mack and Ed Charrier. Mack, known as the gentleman sc... » read more

Why EUV Is So Difficult

By Mark LaPedus - 17 Nov, 2016 - Comments: 23

For years, extreme ultraviolet (EUV) lithography has been a promising technology that was supposed to help enable advanced chip scaling. But after years of R&D, EUV is still not in production despite major backing from the industry, vast resources and billions of dollars in funding. More recently, though, [gettech id="31045" comment="EUV"] lithography appears to be inching closer to pos... » read more

10nm FinFET Market Heats Up

By Mark LaPedus - 16 Oct, 2016 - Comments: 1

The 10nm finFET market is heating up in the foundry business amid the ongoing push to develop chips at advanced nodes. Not long ago, Intel announced its 10nm finFET process, with plans to ramp up the technology in 2017. Then, TSMC recently introduced its 10nm process, with plans to move into production by the fourth quarter of 2016. Now, Samsung Electronics said that it has commenced mass... » read more

7nm Lithography Choices

By Mark LaPedus - 07 Mar, 2016 - Comments: 2

Chipmakers are ramping up their 16nm/14nm logic processes, with 10nm expected to move into early production later this year. Barring a major breakthrough in lithography, chipmakers are using today’s 193nm immersion and multiple patterning for both 16/14nm and 10nm. Now, chipmakers are focusing on the lithography options for 7nm. For this, they hope to use a combination of two technologies ... » read more

1xnm DRAM Challenges

By Mark LaPedus - 18 Feb, 2016 - Comments: 3

At a recent event, Samsung presented a paper that described how the company plans to extend today’s planar DRAMs down to 20nm and beyond. This is an amazing feat. Until very recently, most engineers believed DRAMs would stop scaling at 20nm or so. Instead, Samsung is ramping up the world’s most advanced DRAMs—a line of 20nm parts—with plans to go even further. Micron and SK Hynix soo... » read more

EUV: Cost Killer Or Savior?

By Katherine Derbyshire - 17 Sep, 2015 - Comments: 4

Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process. Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process opt... » read more

Getting Over Overlay

By Mark LaPedus - 18 Jun, 2015 - Comments: 0

Chipmakers continue to migrate to the next node, but there are signs that traditional IC scaling is slowing down. So what’s causing the slowdown? Or for that matter, what could ultimately undo [getkc id="74" comment="Moore's Law"]? It could be a combination of factors. To be sure, IC design costs and complexity are soaring at each node. Scaling challenges are also playing a role. And ov... » read more

Next EUV Challenge: Mask Inspection

By Mark LaPedus - 16 Apr, 2015 - Comments: 2

Extreme ultraviolet ([gettech id="31045" comment="EUV"]) lithography is still not ready for prime time, but the technology finally is moving in the right direction. The EUV light source, for example, is making progress after years of delays and setbacks. Now, amid a possible breakthrough in EUV, the industry is revisiting a nagging issue and asking a simple question: How do you inspect EUV p... » read more

Flash Dance For Inspection And Metrology

By Mark LaPedus - 16 Apr, 2015 - Comments: 0

Chipmakers are moving from planar technology to an assortment of 3D-like architectures, such as 3D NAND and finFETs For these devices, chipmakers face a multitude of challenges in the fab. But one surprising and oft-forgotten technology is emerging as perhaps the biggest challenge in both logic and memory—process control. Process control includes metrology and wafer inspection. Metrolo... » read more

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Knowledge Centers
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