Non-Stateful Logic Gates in ReRAM (RWTH Aachen, FZJ)


A new technical paper titled "Experimental Verification and Evaluation of Non-Stateful Logic Gates in Resistive RAM" was published by researchers at RWTH Aachen University and Forschungszentrum Jülich GmbH (FZJ). Abstract "Resistively switching, non-volatile memory devices facilitate new logic paradigms by combining storage and processing elements. Several non-stateful concepts such as Sco... » read more