Holistic Die-to-Die Interface Design Methodology For 2.5-D Multi-Chip-Module Systems

More than Moore technologies can be supported by system level diversification enabled by chiplet based integrated systems within multi-chip-modules (MCM) and silicon interposer based 2.5D systems. The division of large system-on-chip dies into smaller chiplets with different technology nodes specific to the chiplet application requirement enables the performance enhancement at system level whil... » read more

Architectural Changes Will Drive Miraculous 3D Gains

By Ann Steffora Mutschler Low-Power High-Performance Engineering sat down with Robert Patti, chief technology officer at Tezzaron Semiconductor, to discuss future challenges with regard to 2.5D and 3D design, including making tradeoffs and technical issues specific to 3D design. Tezzaron currently is working on 3D designs. LPHP: What is the starting point technically to achieve the gre... » read more

Getting Ready For Stacked Die

By Ed Sperling The move toward stacking of die has always been a series of disconnected pieces and vague promises for the future, but in the past few months the scenario has changed radically—and so has the commentary. All three of the Big Three EDA vendors now have at least some of the pieces in place for 2.5D stacking and are working on a full 3D flow. Two of the biggest FPGA vendors, A... » read more

Limits For TSVs In 3D Stacks?

By Ed Sperling Semiconductor design always has been about solving technology issues one node at a time, often in the face of a perpetual barrage of looming problems. In fact, if there is any change at all, it’s in the number of threats that have to be solved now at each node, most of them driven by ever-increasing density and the laws of physics. Stacking die holds the promise of becoming... » read more

One-On-One: Aart de Geus

Synopsys' CEO talks with Low-Power Engineering about the future of EDA, the changes in IP, stacked die and 20nm designs. [youtube vid=x9TKRC48OG0] » read more