Week In Review: Manufacturing, Test

By Karen Heyman and Anne Meixner - 30 Sep, 2022 - Comments: 0

Highlights from ITC The hot topic at this week’s International Test Conference (ITC) was tackling silent data corruption, with panel discussions, papers, and Google’s Parthasarathy Ranganathan’s keynote address all emphasizing the urgency of the issue. In the past two years Meta, Google, and Microsoft have reported on silent errors, errors not detected at test, which are adversely impact... » read more

Holistic 3D-IC Interposer Analysis In Product Designs

By Ben Gu - 22 Sep, 2022 - Comments: 1

The miniaturization trend in electronic devices and the rise in smart and IoT device segments make adopting heterogeneous integration of chip components or 3D-ICs a viable option for miniaturization and better interconnection. This vertical stacking of ICs enables the next generation of sophisticated, intelligent devices, necessitating high chip density and terabytes of bandwidth. As per the f... » read more

Designing For Thermal

By Karen Heyman - 13 Sep, 2022 - Comments: 0

Heat has emerged as a major concern for semiconductors in every form factor, from digital watches to data centers, and it is becoming more of a problem at advanced nodes and in advanced packages where that heat is especially difficult to dissipate. Temperatures at the base of finFETs and GAA FETs can differ from those at the top of the transistor structures. They also can vary depending on h... » read more

Enabling Test Strategies For 2.5D, 3D Stacked ICs

By Laura Peters - 08 Sep, 2022 - Comments: 0

Improved testability, coupled with more tests at more insertion points, are emerging as key strategies for creating reliable, heterogeneous 2.5D and 3D designs with sufficient yield. Many changes need to fall into place to make side-by-side 2.5D and 3D stacking approaches cost-effective, particularly for companies looking to integrate chiplets from different vendors. Today, nearly all of t... » read more

Testing The Stack: DFT Is Ready For 3D Devices

By Martin Keim - 08 Sep, 2022 - Comments: 0

When existing advanced 2D designs already push the limits of design-for-test (DFT) tools, what hope do developers have of managing DFT for 3D devices? Can anyone afford the tool run time, on-chip area demand, pattern count, and test time? The answer, from an array of experts, is yes, there is a path to a scalable, affordable, and comprehensive DFT solution for 3D ICs. Well-covered strategies... » read more

Affordable And Comprehensive Testing Of 3D Stacked Die Devices

By Siemens EDA - 07 Sep, 2022 - Comments: 0

Developers of high-end semiconductor products who face manufacturing limitations with respect to die sizes are investing in 3D stacked die technology. These advanced designs already push current design-for-test (DFT) solutions to the limits: tool run time, on-chip area demand, test pattern count, and test time. How then, can designers manage DFT for these new 3D devices? In this paper, we outli... » read more

2.5/3D IC Reliability Verification Has Come A Long Way

By Dina Medhat - 01 Aug, 2022 - Comments: 0

2.5D/3D integrated circuits (ICs) have evolved into an innovative solution for many IC design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the ... » read more

Bespoke Silicon Redefines Custom ASICs

By Ann Mutschler - 28 Jul, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss bespoke silicon and what's driving that customization with Kam Kittrell, vice president of product management in the Digital & Signoff group at Cadence; Rupert Baines, chief marketing officer at Codasip; Kevin McDermott, vice president of marketing at Imperas; Mo Faisal, CEO of Movellus; Ankur Gupta, vice president and general manager of Siemens... » read more

Hybrid Bonding Moves Into The Fast Lane

By Laura Peters - 21 Jul, 2022 - Comments: 1

The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

What Future Processors Will Look Like

By Ed Sperling - 13 Jul, 2022 - Comments: 0

Mark Papermaster, CTO at AMD, sat down with Semiconductor Engineering to talk about architectural changes that are required as the benefits of scaling decrease, including chiplets, new standards for heterogeneous integration, and different types of memory. What follows are excerpts of that conversation. SE: What does a processor look like in five years? Is it a bunch of chips in a package? I... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: 3D-IC

Week In Review: Manufacturing, Test

Holistic 3D-IC Interposer Analysis In Product Designs

Designing For Thermal

Enabling Test Strategies For 2.5D, 3D Stacked ICs

Testing The Stack: DFT Is Ready For 3D Devices

Affordable And Comprehensive Testing Of 3D Stacked Die Devices

2.5/3D IC Reliability Verification Has Come A Long Way

Bespoke Silicon Redefines Custom ASICs

Hybrid Bonding Moves Into The Fast Lane

What Future Processors Will Look Like

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Knowledge Centers
Entities, people and technologies explored