tag: 3D stacking

Playing The Voltage Game
By Ed Sperling - 01 Dec, 2011 - Comments: 0

y Ed Sperling Scaling down the voltage to boost battery life and cut energy costs has always been considered the best option, but it’s getting more difficult at advanced nodes and in stacked die packages. The key problems are noise and leakage. Lowering the voltage exacerbates both of them, forcing a rethinking of the whole design process starting at the architectural level and continuing... » read more

Five Important Changes That Will Affect Power
By Ed Sperling - 03 Nov, 2011 - Comments: 0

By Ed Sperling So far most of the energy savings in SoCs have been achieved using two main approaches—turning off most of the chip most of the time, and changing the materials used to insulate against current leakage. Over the next few years, changes to designs will be more radical, encompass more pieces of a bigger system, and they will be orders of magnitude more effective. From a marke... » read more

Experts At The Table: Mobile Design Challenges
By Ed Sperling - 21 Oct, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss the increasing challenges of designing for mobile devices with Qi Wang, technical marketing group director at Cadence; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Bernard Murphy, CTO of Atrenta; and Dave Reed, senior director of marketing at SpringSoft. What follows are excerpts of that conversation. ... » read more

Low Power Drives Performance And TCO
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Pallab Chatterjee A common theme at this year’s Custom Integrated Circuit Conference was the reduction of power and power management while increasing data throughput. Historically, the show has featured new techniques for ultra high accuracy and brute force improvements in performance at all costs. The main theme this year was that in a world of mobile endpoint devices, the goal is to get... » read more

Executive Briefing: 3D IC Stacking Challenges
By Ed Sperling - 21 Sep, 2011 - Comments: 0

Sonics CEO Grant Pierce sounds off on the challenges of stacking die, what has to change and why. [youtube vid=wCseVs738LQ] » read more

TSVs Ease Heat In 3D ICs
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler In the evolving discussion of 3D ICs and through silicon via (TSV) technology, a key issue engineering teams are facing today is how to reduce the thermal coefficients between substrates in a stacked die. Simply put, what is the best way to get the heat out of the 2.5 or 3D IC? The answer, of course, is anything but simple. “In a 3D system, the heat hierarchy ... » read more

Heat Wreaks Havoc
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler As semiconductor manufacturing technology has scaled ever smaller, the density of power grid networks has caused on-chip temperatures to rise, negatively impacting performance, power, and reliability. CMOS technology, still the predominant material in SoCs, was originally conceived as a low-power technology when compared with the bipolar approach, which was a very... » read more

Experts At The Table: Retrofitting Older Process Nodes
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; Vishal Kapoor, vice president of marketing for SoC realization at Cadence; Naveed Sherwani, CEO of Open-Silicon; John Heinlein, vice president of marketing at ARM; and Jeff Lukanc, director of engineering at IDT. What follows are excerpts of that conversation, which was held in... » read more

3D’s Disruptive And Less-Disruptive Sides
By Ed Sperling - 26 Aug, 2011 - Comments: 0

The momentum behind vertical stacking of die, either in 2.5D or 3D configurations, is growing. So is the argument about just how big a change this will actually represent. To a large extent, it all depends on where you’re sitting. Xilinx CTO Ivo Bolsens calls 3D stacking a disruptive technology. From an FPGA standpoint, which potentially could be used as a programmable addition to any SoC,... » read more

The 3D Power Factor
By Ed Sperling - 26 Aug, 2011 - Comments: 0

In the move to stacked die, one of the biggest issues is power. While chips using leading-edge processes already address this issue effectively through a variety of advanced techniques, the big question mark is what happens with the older technologies. The answer may not be quite so simple. While it’s still possible to use technology developed at older process nodes, it may not be exactly ... » read more

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