tag: 7nm

5nm Design Progress
By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

In-Design Power Rail Analysis
By Ed Sperling - 17 Jul, 2018 - Comments: 0

Tech Talk: Kenneth Chang, senior staff product marketing manager at Synopsys, talks about what can go wrong with power at advanced nodes and why in-design power rail analysis works best early in the flow in helping to reduce overall margin. https://youtu.be/0oiWQPS1-Xk » read more

Defect Reduction At 7/5nm
By Ed Sperling - 12 Jul, 2018 - Comments: 0

Darin Collins, director of metrology at Brewer Science, talks about the cause of defects at advanced nodes and how material purity increasingly plays a role in overall quality and yield. » read more

7nm Design Challenges
By Ed Sperling - 09 Jul, 2018 - Comments: 0

Ty Garibay, CTO at ArterisIP, talks about the challenges of moving to 7nm, who’s likely to head there, how long it will take to develop chips at that node, and why it will be so expensive. This also raises questions about whether chips will begin to disaggregate at 7nm and 5nm. https://youtu.be/ZqCAbH678GE » read more

Market And Tech Inflections Ahead
By Ed Sperling - 27 Jun, 2018 - Comments: 0

Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to talk about the path to autonomous vehicles, industry dis-aggregation and re-aggregation, security issues, and who's going to pay for chips at advanced nodes. SE: All of a sudden we have a bunch of new markets opening up for electronics. We have assisted and autonomous driving, AI and machine learning, v... » read more

Emulation-Driven Implementation
By Ed Sperling - 22 Jun, 2018 - Comments: 0

Tech Talk: Haroon Chaudhri, director of Prime Power at Synopsys, talks about how to shorten time to market and increase confidence in advanced-node designs, while also reducing the amount of guard-banding and improving design freedom. https://youtu.be/xT3CIqjnaBk » read more

Dealing With Resistance In Chips
By Mark LaPedus - 21 Jun, 2018 - Comments: 2

Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Tech Talk: Connected Intelligence
By Ed Sperling - 21 Jun, 2018 - Comments: 0

Gary Patton, CTO at GlobalFoundries, talks about computing at the edge, the slowdown in scaling, and why new materials and packaging approaches will be essential in the future. https://youtu.be/Zbz0R_yFFrQ » read more

Big Trouble At 3nm
By Mark LaPedus - 21 Jun, 2018 - Comments: 0

As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm. Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-p... » read more

Chip Dis-Integration
By Brian Bailey - 14 Jun, 2018 - Comments: 2

Just because something can be done does not always mean that it should be done. One segment of the semiconductor industry is learning the hard way that continued chip integration has a significant downside. At the same time, another another group has just started to see the benefits of consolidating functionality onto a single substrate. Companies that have been following Moore's Law and hav... » read more

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