tag: Accellera

Week In Review: Design, Low Power
By Jesse Allen - 26 Apr, 2019 - Comments: 0

A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

Portable Test and Stimulus Standard Version 1.0
By Accellera - 12 Dec, 2018 - Comments: 0

The definition of the language syntax, C++ library API, and accompanying semantics for the specification of verification intent and behaviors reusable across multiple target platforms and allowing for the automation of test generation is provided. This standard provides a declarative environment designed for abstract behavioral description using actions, their inputs, outputs, and resource depe... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Nov, 2018 - Comments: 0

Tools & Standards Mentor uncorked a PCB design platform for non-specialist PCB engineers focused on multi-dimensional verification. The Xpedition platform can integrate a range of verification tools within a singular authoring environment, providing automatic model creation, concurrent simulation, cross probing from results, and error reviews to identify problems at the schematic or layout... » read more

Week In Review: Design, Low Power
By Jesse Allen - 07 Sep, 2018 - Comments: 0

Cadence teamed up with nine PCB manufacturing partners on an ecosystem to provide easier access to partners' technology files to improve PCB manufacturability. The program, DesignTrue DFM, allows for automated import of a manufacturer's latest DFM rules as well as rule checking in real time as part of the PCB layout process. The nine initial PCB manufactures supporting the program are: Bay Area... » read more

Agile Standards
By Brian Bailey - 08 Aug, 2018 - Comments: 0

Semiconductor Engineering sat down with Lu Dai, chairman for Accellera and senior director of engineering at Qualcomm, to discuss what's changing in standards development. What follows are excerpts of that conversation. SE: Accellera has had a great first half of the year. Dai: Yes, we are only half way through the year and yet we got Portable Stimulus Standard (PSS) out, the SystemC CCI ... » read more

When Bugs Escape
By Brian Bailey - 26 Jul, 2018 - Comments: 0

Bugs are a fact of life, and they always have been. But verification methodologies may not have evolved fast enough to keep up with the growing size and complexity of systems. The types of bugs are changing, too. Some people call these corner cases. Others call them outliers. Still another group refers to them as simulation-resistance superbugs. In markets such as automotive, the notion o... » read more

Week In Review: Design, Low Power
By Jesse Allen - 29 Jun, 2018 - Comments: 0

M&A Siemens acquired Austemper Design Systems, which provides tools for functional safety and safety-critical designs. Founded in 2015, Texas-based Austemper adds state-of-the-art safety analysis, auto-correction and fault simulation technology to address random hardware faults, as well as correct and harden vulnerable areas, subsequently performing fault simulation to ensure the design is... » read more

Wednesday At DAC 2018
By Brian Bailey - 28 Jun, 2018 - Comments: 0

Wednesday starts with a visionary talk followed by a keynote. The Visionary talk was given by Chidi Chidambaram, VP of engineering for Qualcomm, and looked at 'Challenges to Enable 5G System Scaling.' "We have to start taking a system view rather than just following technology and at the same time we have to get concerned about durability," he said. "Mobile will continue to be the leader becaus... » read more

Tuesday At DAC 2018
By Brian Bailey - 27 Jun, 2018 - Comments: 0

The morning starts with the Accellera Breakfast. Accellera has made some significant progress this year and we can expect to hear about the approval of the Portable Stimulus 1.0 specification later in the conference as well as the initial release of SystemC CCI as well as a proposal for the creation of an IP Security Assurance Working Group, which will discuss standards development to address s... » read more

The Week In Review: Design
By Jesse Allen - 22 Jun, 2018 - Comments: 0

Tools Synopsys revealed a power analysis solution for early SoC design as well as signoff-accurate power and reliability closure. PrimePower has reliability as a major focus, expanding power and reliability signoff and ECO closure capabilities from physical awareness to cell electromigration effects. Supported power types include peak power, average power, clock network power, leakage power, a... » read more

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