Chip Industry Week in Review

By The SE Staff - 02 Aug, 2024 - Comments: 0

Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML. Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government... » read more

Chip Security Now Depends On Widening Supply Chain

By Ann Mutschler - 01 Aug, 2024 - Comments: 0

Securing chips is becoming more challenging as SoCs are disaggregated into chiplets, creating new vulnerabilities that involve hardware and software, as well as multiple entities, and extending threats across a much broader supply chain. In the past, much of the cyber threat model was confined to either hardware or software, and where multiple vendors were involved, various chips were separa... » read more

The Journey Of The Olympic Torch: History, Design, And Technology

By Reela Samuel - 01 Aug, 2024 - Comments: 0

The Olympic Torch represents a rich, blended history of ancient traditions and modern values. Bearing the iconic flame, the Olympic torch relay honors the symbolic power of fire, embodying purity, passion, and perseverance. The flame ignites in Olympia, Greece, through the sun's rays—linking the ancient and modern Games—and journeys to the host city, where it illuminates the "Celebration Ca... » read more

Blog Review: July 31

By Jesse Allen - 31 Jul, 2024 - Comments: 0

Cadence's Jasmine Makhija explains how to boost the performance of CXL 3.0 by using NOP (No Operation) Insertion Hints in latency-optimized 256B Flit Mode, which enables the system to quickly revert to the low-latency path after temporarily switching to a higher-latency path due to error correction needs. Synopsys' Robert Fey finds that by automatically and dynamically linking requirements a... » read more

Aeroacoustics Large-Eddy Simulation of VTOL Aircraft Design

By Cadence - 31 Jul, 2024 - Comments: 0

This conference paper, co-authored by Honda Motor Co. and Cadence, reveals findings on the aeroacoustics predictions of multibladed vertical take-off and landing (VTOL) rotors using large-eddy simulations (LES). Why should you read this white paper? Advanced Simulations: We conducted simulations on VTOL rotors with two to five blades, assessing high-frequency noise predictions. Exp... » read more

Will AI Disrupt EDA?

By Brian Bailey - 25 Jul, 2024 - Comments: 1

Generative AI has disrupted search, it is transforming the computing landscape, and now it's threatening to disrupt EDA. But despite the buzz and the broad pronouncements of radical changes ahead, it remains unclear where it will have impact and how deep any changes will be. EDA has two primary roles — automation and optimization. Many of the optimization problems are NP hard, which means ... » read more

Floor-Planning Evolves Into The Chiplet Era

By Karen Heyman - 25 Jul, 2024 - Comments: 0

3D-ICs and heterogeneous chiplets will require significant changes in physical layout tools, where the placement of chiplets and routing of signals can have a big impact on overall system performance and reliability. EDA vendors are well aware of the issues and working on solutions. Top on the list of challenges for 3D-ICs is thermal dissipation. Logic typically generates the most heat, and ... » read more

Debugging SystemVerilog Constraint Randomization: A Comprehensive Guide

By Rich Chang - 25 Jul, 2024 - Comments: 0

SystemVerilog constraint randomization is a powerful methodology for generating realistic and diverse test scenarios in the realm of hardware design verification. However, like any complex methodology, it can sometimes be challenging to debug when an unexpected issue arises. In this article, we will explore common debug techniques and strategies to help you effectively troubleshoot your SystemV... » read more

PCIe 6.0 Address Translation Services: Verification Challenges And Strategies

By Geeta Arora - 18 Jul, 2024 - Comments: 0

Address Translation Services (ATS) is a mechanism in PCIe that allows devices to request address translations from the Input/Output Memory Management Unit (IOMMU). This is particularly important where devices need to access virtual memory. ATS enhances performance by enabling devices to cache translations, reducing the latency associated with memory access. This blog delves into the semantics ... » read more

IC Power Optimization Required, But More Difficult To Achieve

By Adam Kovac - 18 Jul, 2024 - Comments: 0

Power optimization is playing an increasingly vital role in chip and chip and system designs, but it's also becoming much harder to achieve as transistor density and system complexity continue to grow. This is especially evident with advanced packages, chiplets, and high-performance chips, all of which are becoming more common in complex designs. Inside data centers, racks of servers are str... » read more

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Knowledge Centers
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Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

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