Week In Review: Auto, Security, Pervasive Computing


Tesla will recall 362,000 U.S. vehicles over Full Self-Driving (FSD) Beta software after the National Highway Traffic Safety Administration (NHTSA) found that the cars sometimes have unsafe behavior around intersections when using the FSD Beta system. Examples are “traveling straight through an intersection while in a turn-only lane, entering a stop sign-controlled intersection without coming... » read more

Blog Review: Feb. 15


Siemens EDA's Harry Foster examines the relationship between verification maturity and non-trivial bug escapes into production, as well as whether safety critical development processes yield higher quality in terms of preventing bugs and achieving silicon success. Synopsys' Shankar Krishnamoorthy finds that the rapid progress of machine learning models is driving demand for more domain-speci... » read more

Simplifying Integration And Security In Home Networks


An explosion of devices connected to the internet is driving vendors to implement standards that simplify the initial setup and improve security and integration with other devices, regardless of brand, network protocols, or country of origin. Farthest along in this multi-ecosystem merge is the Connectivity Standards Alliance (CSA), which today is supported by more than 500 companies, includi... » read more

Week In Review: Design, Low Power


Arm is heading for an IPO this year, with plans "fairly well developed and underway now," CEO Rene Haas told Reuters. Arm reported fiscal Q3 revenue of $746 million, up 28% compared with the same period in 2021, setting the stage for a public offering. The company noted it had double- or triple-revenue increases in automotive, consumer, infrastructure, and IoT. The Si2 Compact Model Coalit... » read more

Chiplets Taking Root As Silicon-Proven Hard IP


Chiplets are all the rage today, and for good reason. With the various ways to design a semiconductor-based system today, IP reuse via chiplets appears to be an effective and feasible solution, and a potentially low-cost alternative to shrinking everything to the latest process node. To enable faster time to market, common IP or technology that already has been silicon-proven can be utilized... » read more

Unified AI/ML Solution Helps Accelerate Verification Curve


With the surge in usage requirements and increasing customer demands, hardware design is quickly becoming more complex. The rapid change in market trends, with a greater focus on technologies such as electric vehicles, dictates the demand for efficient power management and high-performance processing. Verification throughput continues to be a bottleneck as SoC designs increase in size, and so d... » read more

Blog Review: Feb. 8


Cadence's Sanjeet Kumar points to key changes and optimizations that are done for USB3 Gen T compared to USB3 Gen X tunneling in order to minimize tunnel overhead and maximize USB3 throughput. Siemens EDA's Harry Foster considers the effectiveness of IC and ASIC verification by looking at schedule overruns, number of required spins, and classification of functional bugs. Synopsys' Chris C... » read more

Chip Industry’s Earnings Roundup


Editor's Note: Updated throughout February 2023 for additional earnings releases. Many companies reported revenue growth in the most recent quarter, but the latest round of chip industry earnings releases reflected some major themes: Demand for consumer electronics softened due to inflation, rising interest rates, and post-pandemic market saturation, creating a slump in the memory chip ... » read more

Week In Review: Semiconductor Manufacturing, Test


Imec released its semiconductor roadmap, which calls for doubling compute power every six months to handle the data explosion and new data-intensive problems. Imec named five walls (scaling, memory, power, sustainability, cost) that need to be dismantled. The roadmap (below) stretches from 7nm to 0.2nm (2 angstroms) by 2036, and includes four generations of gate-all-around FETs followed by thre... » read more

Week in Review: Design, Low Power


Intel discontinued its Pathfinder for RISC-V program, according to numerous reports. The program provided a pre-silicon development environment to support IP selection and early-stage software development using Intel FPGA and simulator platforms. "Since Intel will not be providing any additional releases or bug fixes, we encourage you to promptly transition to third-party RISC-V software tools ... » read more

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