tag: DFT

More Manufacturing Issues, More Testing
By Ed Sperling - 08 Feb, 2022 - Comments: 0

Douglas Lefever, CEO of Advantest America, sat down with Semiconductor Engineering to talk about changes in test, the impact of advanced packaging, and business changes that are happening across the flow. What follows are excerpts of that discussion. SE: What are the big changes ahead in test? Lefever: It's less about inflection points and more like moving from algebra to calculus in the ... » read more

Comprehensive Model of Electron Conduction in Oxide-Based Memristive Devices
By Technical Paper Link - 03 Feb, 2022 - Comments: 0

Abstract "Memristive devices are two-terminal devices that can change their resistance state upon application of appropriate voltage stimuli. The resistance can be tuned over a wide resistance range enabling applications such as multibit data storage or analog computing-in-memory concepts. One of the most promising classes of memristive devices is based on the valence change mechanism in oxide... » read more

Veloce Coverage App And Veloce Assertion App Deliver Unified Coverage Methodology
By Siemens EDA - 26 Jan, 2022 - Comments: 0

The interoperability of the Veloce Coverage app and the Veloce Assertion app with other verification engines (simulation and formal) enables merging coverage collected by each engine and provides a cohesive coverage closure report and analysis flow. It enables the verification team and product-level management to make important decisions such as coverage closure sign-off, test quality analysis ... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part I
By Rahul Singhal - 11 Jan, 2022 - Comments: 0

The traditional processors designed for general-purpose applications struggle to meet the computing demands and power budgets of artificial intelligence (AI) or machine leaning (ML) applications. Several semiconductor design companies are now developing dedicated AI/ML accelerators that are optimized for specific workloads such that they deliver much higher processing capabilities with much low... » read more

Streaming Scan Network: An Efficient Packetized Data Network For Testing Of Complex SoCs
By Siemens EDA - 07 Dec, 2021 - Comments: 0

Originally presented at the 2020 International Test Conference by Siemens and Intel authors, this paper describes the Tessent Streaming Scan Network technology and demonstrates how this packetized data network optimizes test time and implementation productivity for today’s complex SoCs. The author-submitted version of the IEEE paper is reprinted here with permission. Authors: Jean-Françoi... » read more

Success Stories For Packetized Scan Data
By Geir Eide - 07 Dec, 2021 - Comments: 0

Some new design-for-test (DFT) technologies are difficult, expensive, or risky to implement but offer significant benefits. Other technologies are easy to implement but offer minor improvements. The calculation of whether (or when) to adopt new technology includes consideration of the pressures of DFT today—design complexity, the lack of flexibility in hardwiring scan channels, the proliferat... » read more

Missing Interposer Abstractions And Standards
By Brian Bailey - 29 Nov, 2021 - Comments: 0

The design and analysis of an SoC based on an interposer is not for the faint of heart today, but the industry is aware of the challenges and is attempting to solve them. Until that happens, however, it will be a technique that only large companies can deploy because they need to treat everything almost as if it were a single die. The construction of large systems uses techniques, such as ab... » read more

Don’t Let X Be A Problem For Logic BIST
By Rahul Singhal - 12 Oct, 2021 - Comments: 0

By Rahul Singhal and Giri Podichetty A failure in the operation of integrated circuits (ICs) or chips deployed in safety-critical applications such as automotive, medical, and aerospace could have catastrophic consequences. These failures could stem from defects in the chip that escaped manufacturing tests or from transient faults that can occur during system operation due to factors such as... » read more

How To Maximize Your Competitiveness In The Semiconductor Industry Using Advanced DFT
By Siemens EDA - 07 Sep, 2021 - Comments: 1

Embarking on advanced SoCs without a smart design-for-test (DFT) strategy can be harmful to your bottom line. Being competitive in today’s semiconductor market means adopting integrated, scalable, and flexible solutions to cut DFT implementation time, test costs, and time-to-market. Tessent DFT technologies, developed in partnership with industry leaders, provide the most advanced DFT and yie... » read more

The Era Of Packetized Scan Test Has Arrived
By Geir Eide - 07 Sep, 2021 - Comments: 0

For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression became the norm to address test data time and volume. Over the last decade, hierarchical DFT enabled DFT engineers to apply a divide and conquer on large design, improving both implementation effort and... » read more

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