Cut Power + Cost 5 – 10x: Integrate FPGA In Your SoC

FPGA chips are high cost devices with a high profit margin for the manufacturer: this goes away when you integrate. FPGA packages are large and expensive because of the large number of very high speed signals that require expensive signal integrity design and packaging layers. When you integrate this goes away. And you save the board area the FPGA package took; and eliminate expensive voltage r... » read more

A HIL Methodology For The SoC Development Flow

A technical paper titled “Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap” was published by researchers at University of Bremen and German Research Center for Artificial Intelligence (DFKI). Abstract: "Virtual Prototypes act as an executable specification model, offering a unified behavior reference model for SW and HW engineers. However, b... » read more

FPGA-Proven RISC-V System With Hardware Accelerated Task Scheduling

A technical paper titled “Enabling HW-based Task Scheduling in Large Multicore Architectures” was published by researchers at Barcelona Supercomputing Center, University of Campinas, University of Sao Paulo, and Arteris Inc. Abstract: "Dynamic Task Scheduling is an enticing programming model aiming to ease the development of parallel programs with intrinsically irregular or data-dependent... » read more

Applying Machine Learning to EDA, FPGA Design Automation Tools

A technical paper titled “Application of Machine Learning in FPGA EDA Tool Development” was published by researchers at the University of Texas Dallas. Abstract: "With the recent advances in hardware technologies like advanced CPUs and GPUs and the large availability of open-source libraries, machine learning has penetrated various domains, including Electronics Design Automation (EDA). E... » read more

Neuromorphic Hardware Accelerator For Heterogeneous Many-Accelerator SoCs

A technical paper titled “SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip” was published by researchers at Columbia University. Abstract: "Neuromorphic computing is an emerging field with the potential to offer performance and energy-efficiency gains over traditional machine learning approaches. Most neuromorphic hardware, however, has been designed wi... » read more

Framework for Prototyping And In-Hardware Evaluation of Post-Quantum Cryptography HW Accelerators (TU Darmstadt)

A technical paper titled “PQC-HA: A Framework for Prototyping and In-Hardware Evaluation of Post-Quantum Cryptography Hardware Accelerators” was published by researchers at TU Darmstadt. Abstract: "In the third round of the NIST Post-Quantum Cryptography standardization project, the focus is on optimizing software and hardware implementations of candidate schemes. The winning schemes are ... » read more

A RISC-V Capability Architecture Orchestrating Compiler, Architecture, And System Designs For Full Memory Safety (Georgia Tech, Arm Research)

A technical paper titled “RV-CURE: A RISC-V Capability Architecture for Full Memory Safety” was published by researchers at Georgia Institute of Technology and Arm Research. Abstract: "Despite decades of efforts to resolve, memory safety violations are still persistent and problematic in modern systems. Various defense mechanisms have been proposed, but their deployment in real systems re... » read more

Embedded GPU for FPGA, Achieving Over 770 MHz Operating Frequency With Unconstrained Compile

A technical paper titled “eGPU: A 750 MHz Class Soft GPGPU for FPGA” was published by researchers at Intel Corporation and Imperial College London. Abstract: "This paper introduces the eGPU, a SIMT soft processor designed for FPGAs. Soft processors typically achieve modest operating frequencies, a fraction of the headline performance claimed by modern FPGA families, and obtain correspondi... » read more

CNN Hardware Architecture With Weights Generator Module That Alleviates Impact Of The Memory Wall

A technical paper titled “Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation” was published by researchers at Samsung AI Center and University of Cambridge. Abstract: "The unprecedented accuracy of convolutional neural networks (CNNs) across a broad range of AI tasks has led to their widespread deployment in mobile and embedded settings. In a pursuit for high... » read more

A Hardware Accelerator Designed For The Homomorphic SEAL-Embedded Library

A technical paper titled "VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library" was published by researchers at University of Pisa. Abstract: "Homomorphic Encryption (HE) allows performing specific algebraic computations on encrypted data without the need for decryption. For this reason, HE is emerging as a strong privacy-preserving solution... » read more

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