Cut Power+Cost 5–10x: Integrate FPGA In Your SoC

You can integrate an FPGA in an SoC at full speed and flexibility. Until EFLX eFPGA, it was not possible to integrate full-speed, high-density FPGA in an SoC. Now you can. Click here to read more. » read more

Accelerate Complex Algorithms With Adaptable Signal Processing Solutions

Technology is continuously advancing and exponentially increasing the amount of data produced. Data comes from a multitude of sources and formats, requiring systems to process different algorithms. Each of these algorithms present their own challenges including low-latency and deterministic processing to keep up with incoming data rates and rapid response time. Considering that many of these se... » read more

FPGA-Based HW/SW Platform For Pre-Silicon Emulation Of RISC-V Designs (Barcelona Supercomputing Center)

A technical paper titled “Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs” was published by researchers at Barcelona Supercomputing Center and Universitat Politècnica de Catalunya. Abstract: "Emulating chip functionality before silicon production is crucial, especially with the increasing prevalence of RISC-V-based designs. FPGAs are promising candidate... » read more

Expand Your Semiconductor’s Market With Programmable Data Planes

In nearly every communication interface today, many challenges exist. Not only must networks manage high volumes of data traffic, they must also be highly aware of malicious data intrusions. With increasing data moving though these networks, combined with demand for faster response times and lower latency, high performance packet processors came into existence as these were the only mechanisms ... » read more

Security Threats To Multitenant FPGAs: A Remote Undervolting Attack That Activates A Trojan Concealed Within A Victim Design 

A technical paper titled “X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs” was published by researchers at EPFL, Cyber-Defence Campus (Switzerland), and Northwestern Polytechnical University (China). Abstract: "Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability ... » read more

How Secure Are FPGAs?

The unique hybrid software/hardware nature of FPGAs makes them tempting targets for cyberattacks, while also enabling them to rebuff attacks and change the attack surface before significant damage can be done. But it's becoming increasingly challenging to address all the potential vulnerabilities. FPGAs are often included in larger systems, each with their own unique attack vectors as well a... » read more

Environmentally Sustainable FPGAs (Notre Dame, Univ. of Pittsburgh)

A new technical paper titled "REFRESH FPGAs: Sustainable FPGA Chiplet Architectures" was published by University of Notre Dame and University of Pittsburgh. Abstract "There is a growing call for greater amounts of increasingly agile computational power for edge and cloud infrastructure to serve the computationally complex needs of ubiquitous computing devices. Thus, an important challenge i... » read more

Hardware-Based Methodology To Protect AI Accelerators

A technical paper titled “A Unified Hardware-based Threat Detector for AI Accelerators” was published by researchers at Nanyang Technological University and Tsinghua University. Abstract: "The proliferation of AI technology gives rise to a variety of security threats, which significantly compromise the confidentiality and integrity of AI models and applications. Existing software-based so... » read more

Cut Power + Cost 5 – 10x: Integrate FPGA In Your SoC

FPGA chips are high cost devices with a high profit margin for the manufacturer: this goes away when you integrate. FPGA packages are large and expensive because of the large number of very high speed signals that require expensive signal integrity design and packaging layers. When you integrate this goes away. And you save the board area the FPGA package took; and eliminate expensive voltage r... » read more

A HIL Methodology For The SoC Development Flow

A technical paper titled “Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap” was published by researchers at University of Bremen and German Research Center for Artificial Intelligence (DFKI). Abstract: "Virtual Prototypes act as an executable specification model, offering a unified behavior reference model for SW and HW engineers. However, b... » read more

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