tag: IBM

Experts At The Table: Multipatterning
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Ele... » read more

CNSE Readying NFX Fab for G450C, EUV Efforts
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By David Lammers Two key areas of the semiconductor industry’s future—the 450mm wafer transition and EUV lithography—are the focus of the new NFX (NanoFab Xtension) building now under construction at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. [caption id="attachment_6322" align="alignright" width="120" caption="Alain Kaloyeros"][/caption] T... » read more

Challenges Mount For Interconnect
By Mark LaPedus - 26 Jun, 2012 - Comments: 0

By Mark LaPedus There are a plethora of chip-manufacturing challenges for the 20nm node and beyond. When asked what are the top challenges facing leading-edge chip makers today, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, said it boils down to two major hurdles: lithography and the interconnect. The problems with lithography are well documented.... » read more

Fabless-Foundry Model Under Stress
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Mark LaPedus The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond. Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography. ... » read more

Power Shift
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ed Sperling For the past decade, most of the real gains in energy efficiency were developed for chips inside mobile electronics because of the demand for longer battery life. Dark silicon now represents the majority of mobile devices, multiple power islands are commonplace to push many functions into deep sleep, and performance is usually the secondary concern for most applications. Whil... » read more

The Hidden Costs Of Directed Self-Assembly
By Ed Sperling - 29 May, 2012 - Comments: 2

By Mark LaPedus Directed self-assembly (DSA) has been billed by some as a potential paradigm shift in semiconductor manufacturing, but it may not turn out to be quite the panacea its proponents suggest—or at least not yet. There are many questions surrounding DSA, an alternative lithography technology that makes use of block copolymers to enable fine pitches. Key among those questions ar... » read more

ASMC: TSVs Needed as Scaling Challenges Mount
By Ed Sperling - 29 May, 2012 - Comments: 0

By David Lammers With the industry facing challenges in the introduction of EUV lithography and high costs for double patterning, TSV introductions have taken on heightened importance, participants said at the SEMI Advanced Semiconductor Manufacturing Conference (ASMC), held in Saratoga Springs, N.Y. in mid-May. Risto Puhakka, president of market research firm VLSI Research Inc., said the g... » read more

New Processes Define New Power Plans
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Pallab Chatterjee FinFETs, stacked die, heterogeneous interposers, TSVs, 450mm wafers, new interconnects and everything with MEMs and sensors is what the last few weeks have brought. A number of major announcements, technology releases, conference updates have identified these technologies as the future of IC design. At ISQED, Robert Geer, chief academic officer at the College of Nanosca... » read more

Consortium Results (Part 3 of 3): 20nm FDSOI Comes Out Way Ahead
By Various Writers - 27 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ The SOI Industry Consortium announcement at the end of the year provided silicon proof that FD-SOI handily bea... » read more

Coherency Becomes A Stack Of Issues
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling As complexity increases and the industry increasingly shifts away from ASICs to SoCs, the concept of coherency is beginning to look more like a stack of issues than a discrete piece of the design. There are at least five levels of coherency that need to be considered already, with more likely to surface as stacked die become mainstream over the next few years. Perhaps even mo... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy